I am a fifth-year PhD student in electrical engineering at Stanford advised by Mark Horowitz. I received my B.S. in Electrical Engineering and Business, Economics, and Management from Caltech in 2019 and my M.S. in Electrical Engineering from Stanford in 2021. My research is supported by the Quad Fellowship (2023 to 2024) and Stanford's Knight-Hennessy Graduate Fellowship (2019 to 2022).

I am broadly interested in hardware design for cryptography and machine learning applications. I am curious about the security implications of enabling faster execution of cryptographic protocols and worked on designing a fast extended GCD algorithm and accelerator for constant-time modular inversion and verifiable delay functions. On the machine learning side, I am working on dynamically adapting the execution of state-of-the-art models for use in real-time systems and am working on accelerating dynamic transformer models for computer vision in an ongoing collaboration with NVIDIA. I previously worked on building a flexible memory generator as part of an agile software-hardware co-design flow with Stanford's Agile Hardware (AHA) Project. As part of my research, I have worked on taping out chips in SKY130nm, TSMC16nm, and GF12nm. During the summer, I have interned with Meta Reality Labs, NVIDIA's Architecture Research Group, Apple, Microsoft, and Intel.

I am a PhD candidate in the Department of Electrical and Computer Engineering at the University of British Columbia, advised by Prof. Tor Aamodt. My Ph.D. thesis is on Energy-Efficient Acceleration for Autonomous Robotics. I have worked on algorithm-hardware co-optimization for robot perception and planning. My primary research area is Computer Architecture, and I have been focusing on building better computing platforms for deep learning and robotics tasks.

Before joining PhD, I worked in Qualcomm as a part of the VLSI Design Team. I received my master's in Microelectronics and VLSI from the Indian Institute of Technology Bombay, and I received a Silver Medal and Best Thesis Award for my academic performance and research contributions.

I am currently in the Job market and actively looking for research positions!

I'm Gelara, a forward-thinking computer architecture master's student from Iran. My focus lies in Approximate Computing, Bio-inspired Computing, and Brain Interface Computing.

Vijayalakshmi Saravanan received her Ph.D. in Computer Science and Engineering from VIT University, India under Erasmus Mundus Fellowship (EURECA) as research exchange student at Mälardalen University, Sweden and visiting researcher at Ryerson University, Canada. She is currently an Assistant Professor in Practice at University of Texas, San Antonio (UTSA) in the department of Computer Science. Prior to this, she was a Postdoctoral Associate at UB (University at Buffalo), The State University of New York, USA and University of Waterloo, Canada under the prestigious “Schlumberger Faculty for the Future” Fellowship award (2015-2017). She is having 10 years of teaching experience in two premier Universities VIT and Amrita Vishwa Vidyapeetham, India. Dr. Saravanan has published many technical articles in scholarly international journal and conferences. She is serving as technical reviewer and program committee member for reputed conference & journals such as GHC, SIGCSE and Springer. Her research interests include Power-Aware Processor Design, Big Data, IoT and Computer Architecture. She is a Senior Member of IEEE & ACM, CSI, Ex-Chair for IEEE-WIE VIT affinity group, India (2009-2015), NPA (National Postdoctoral Association) Annual Meetings committee, Workshop/IIA Co-Chair (2017-2018) Poster committee Co-chair (2018-2019) and a Board member of N2WOMEN (Networking Networking Women).