For decades, Moore’s Law and its partner Dennard Scaling have driven technology trends that have enabled exponential performance improvements in computer systems at manageable power dissipation. With the slowing of Moore/Dennard improvements, designers have turned to a range of approaches for extending scaling of computer systems performance and power efficiency. Unfortunately, these scaling gains come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability. My work explores the way forward for computer systems designers in this “Post-ISA” era of shifting abstractions. My group looks hardware and software design issues for specialization/heterogeneity and methods for formal verification. We are also increasingly focused on the hardware/software systems issues of Quantum Computing.

I am a PhD Student at Chalmers University of Technology in Gothenburg, Sweden under the guidance of Professor Per Stenström. My research focuses on GPU architectures for approximate computing systems.

Vijayalakshmi Saravanan received her Ph.D. in Computer Science and Engineering from VIT University, India under Erasmus Mundus Fellowship (EURECA) as research exchange student at Mälardalen University, Sweden and visiting researcher at Ryerson University, Canada. She is currently an Assistant Professor in Practice at University of Texas, San Antonio (UTSA) in the department of Computer Science. Prior to this, she was a Postdoctoral Associate at UB (University at Buffalo), The State University of New York, USA and University of Waterloo, Canada under the prestigious “Schlumberger Faculty for the Future” Fellowship award (2015-2017). She is having 10 years of teaching experience in two premier Universities VIT and Amrita Vishwa Vidyapeetham, India. Dr. Saravanan has published many technical articles in scholarly international journal and conferences. She is serving as technical reviewer and program committee member for reputed conference & journals such as GHC, SIGCSE and Springer. Her research interests include Power-Aware Processor Design, Big Data, IoT and Computer Architecture. She is a Senior Member of IEEE & ACM, CSI, Ex-Chair for IEEE-WIE VIT affinity group, India (2009-2015), NPA (National Postdoctoral Association) Annual Meetings committee, Workshop/IIA Co-Chair (2017-2018) Poster committee Co-chair (2018-2019) and a Board member of N2WOMEN (Networking Networking Women).

Jing (Jane) Li is a Dugald C. Jackson Assistant Professor in the department of Electrical and Computer Engineering and Computer Science (affiliated) the University of Wisconsin – Madison. She is part of Computer Architecture @ UW-Madison and Machine Learning @ UW-Madison. She is one of the PIs in SRC JUMP center – Center for Research on Intelligent Storage and Processing-In-Memory (CRISP). She spent her early career at IBM T. J. Watson Research Center as a Research Staff Member after obtaining her PhD degree from Purdue University in 2009. She is broadly interested in the big problems in computer system across the full stack. She is also a passionate computer experimentalist and enjoy building real computer systems (both hardware and software). In particular, she has made contributions to the following “memory-centric” areas: 1) domain-specific accelerator and its interaction with emerging memories (HMC/HBM/NVM), 2) programmable in-memory computing architecture enabled by emerging nonvolatile memories (PCM/RRAM/STT RAM), 3) system support (e.g., virtualization) for accelerators (e.g., FPGA), and 4) FPGA-based full system simulation infrastructure (MEG) for memory system research. A summary of her research can be found at https://wicil.ece.wisc.edu/research/. A research vision on the importance of interaction between machine learning and computer system can be found at our white paper (co-authored with a number of great researchers in both fields).

One key differentiator of her research is that besides modeling and simulations, she put strong emphasis on real hardware demonstration through architecting, designing and testing new prototypes, both at chip level and system level. The systems that she built with her students have achieved several key milestones, including a scalable graph analytics system ranked No. 1 on the GreenGraph500 list, a deep learning system that set the world-record in performance and energy efficiency for accelerating dense convolutional neural network using FPGA. She and her research team has also taped out several new computer chips with complete system support (programming model, runtime, virtualization, API, etc.) that are built with post-CMOS nonvolatile memory technology (e.g., RRAM) integrated with silicon CMOS through monolithic 3D integration, including Liquid Silicon which won DARPA Young Faculty Award (one out of 2 in computer area and one out of 26 across all areas nationwide, the first awardee in computer engineering and computer science at UW-Madison), and Two-Dimensional Associative Processor which won NSF CAREER Award, in addition to the first fabricated in-memory processing chip for search and a variable-bit storage chip that I built at IBM which won IBM's highest technical achievement award, the IBM's CEO Milestone.