Our
Mission
Women in Computer Architecture (WICARCH) is designed to create a community for women studying and working in the field of computer architecture. Our goal is to promote women in computer architecture and increase visibility for their research and development contributions. We welcome participation from all women including students, post docs, industry researchers and developers and faculty members. To be listed in our directory, please click here.
Profiles of WICArch
The mission of this section is to profile women in computer architecture across many walks of our field, from [junior, senior] x [industry, academia].
If you would like to be profiled, would like to nominate someone to be profiled, or would like to write a profile, please let us know by wicarch-chair@acm.org
Mengjia Yan
Dr. Mengjia Yan is undoubtedly one of the most delightful people you will ever meet – smart, positive, exceedingly wise beyond her years, and the kind of person who can turn a frown upside down. She was paired with me as a mentee at ISCA 2018, but I genuinely think that it is I who have benefited from the relationship. These days, she is a new assistant professor at MIT, having recently completed her PhD at the University of Illinois at Urbana-Champaign in 2019.
WICArch Directory
We actively maintain a list of women working in the field of computer architecture. The goal of this list is many-fold. First, the list services as a resource for program chairs and conference organizers to identify women to serve in key technical roles such as keynote, panels and program committees. Second, the list is designed to foster community and help women connect with other women in computer architecture. This list can be used by current and potential graduate students to find advisors and mentors. Four profiles, selected randomly, are shown below. We encourage you to browse the full directory.
Pantea Zardoshti
Senior Research SDE
Microsoft
Personal URL
Kavya Sreedhar
Graduate Student
Stanford University
Personal URL
I am a fifth-year PhD student in electrical engineering at Stanford advised by Mark Horowitz. I received my B.S. in Electrical Engineering and Business, Economics, and Management from Caltech in 2019 and my M.S. in Electrical Engineering from Stanford in 2021. My research is supported by the Quad Fellowship (2023 to 2024) and Stanford's Knight-Hennessy Graduate Fellowship (2019 to 2022).
I am broadly interested in hardware design for cryptography and machine learning applications. I am curious about the security implications of enabling faster execution of cryptographic protocols and worked on designing a fast extended GCD algorithm and accelerator for constant-time modular inversion and verifiable delay functions. On the machine learning side, I am working on dynamically adapting the execution of state-of-the-art models for use in real-time systems and am working on accelerating dynamic transformer models for computer vision in an ongoing collaboration with NVIDIA. I previously worked on building a flexible memory generator as part of an agile software-hardware co-design flow with Stanford's Agile Hardware (AHA) Project. As part of my research, I have worked on taping out chips in SKY130nm, TSMC16nm, and GF12nm. During the summer, I have interned with Meta Reality Labs, NVIDIA's Architecture Research Group, Apple, Microsoft, and Intel.
Accelerator-Based, Application-Specific and Reconfigurable Architecture, Architectural Support For Security Or Virtualization, Iot, Mobile and Embedded Architecture
Poona Bahrebar
Postdoctoral Research Fellow
University of California, Irvine
Personal URL
I am currently a Post-Doctoral Research Fellow at University of California, Irvine with the prestigious Fellowship Award received from the Belgian-American Educational Foundation (BAEF).
I received my PhD degree in Computer Science Engineering at Ghent University, Belgium in 2017 with a thesis on "Adaptive Routing Algorithms in Networks-on-Chip", and stayed as a Post-Doctoral Researcher at the Department of Electronics and Information Systems until Dec. 2019.
I am the recipient of the Best Paper Award at the 11th International Workshop on Network-on-Chip Architectures (NoCArc) in Oct. 2018. Moreover, I serve as the TPC member and reviewer of several international conferences and journals.
Interconnection Network, Router and Network Interface Architecture
Charu
PhD Candidate
Northeastern University
Personal URL
Charu Kalra is a PhD student in the Computer Engineering Department at Northeastern University. She is part of the Northeastern University Computer Architecture Research (NUCAR) group under the direction of Prof. David Kaeli. Her research interests include GPU compilers, software reliability, machine learning, workload characterization, and performance evaluation of GPU systems. Her PhD thesis focuses on design and evaluation of compiler-based techniques to predict and improve reliability of GPU applications. In 2014, Charu was featured on NVIDIA's 'Women Who CUDA' list. She has also pursued internships at AMD and AMD Research in the past.
Accelerator-Based, Application-Specific and Reconfigurable Architecture, Dependable Architecture, Instruction, Thread and Data-Level ParallelismInitiatives
We organize various initiatives to better connect women in computer architecture.
Join Our Mailing List
2. Update your gender in your myACM account (create/activate account as needed)
Join Our Slack Channel
We offer an informal mentoring program through our slack channel (wicarch.slack.com). Women at all career stages are encouraged to join. The mentoring program provides an easy way to connect with other women and receive advice on a wide range of career and personal issues.
If you need assistance in joining our mailing list or slack channel, please send email to wicarch-chair@acm.org.
This website serves women in the field of computer architecture.
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