Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne.

My research focuses on bridging the gap between software and hardware with the purpose of building efficient circuits for Field Programmable Gate Arrays (FPGAs). I develop new high-level synthesis (HLS) techniques: the purpose is to generate hardware designs from high-level programming languages and to enable software developers to build efficient accelerators. I aim to change the HLS paradigm so that the produced circuits share key features with modern superscalar processors and are able to handle important classes of irregular and control-dominated applications.

I am grateful to have received the Google PhD Fellowship, the EPFL EDIC Fellowship, and the Google Anita Borg (Women Techmakers) Scholarship.

I am an Assistant Professor in Computer Science and Engineering at Arizona State University (ASU). I am also the Associate Director of the NSF I/UCRC Center for Embedded Systems (CES). Before joining ASU, I held a number of industrial internship positions with Intel, IBM, and Google. I am a senior member of both ACM and IEEE.

My research area lies in Computer and System Architectures. In particular, my research interests include high-performance and energy-efficient computer architectures through

• hardware heterogeneity,
• energy harvesting techniques for emerging computing devices,
• temperature and energy management for portable electronics,
• performance characterization, analysis and prediction, and
• memory subsystem designs.

I am the recipient of the 2017 NSF CAREER Award, the 2017 IEEE Young Engineer of the Year Award, the 2014 IEEEE Best of Computer Architecture Letter Award, the 2013 Science Foundation of Arizona Bisgrove Early Career Award, and the 2011-12 Intel Ph.D. Fellowship Award. My research has been supported by both industry sources and the National Science Foundation to a level over $1.8 million.

I serve on the Executive Committee of the IEEE Technical Committee on Computer Architecture from 2017-19 and am the Program Chair for the IEEE International Symposium on Workload Characterization, 2018. I completed my M.A. and Ph.D. degrees in Electrical Engineering from Princeton University in 2008 and 2012, respectively, and received a B.Sc. degree in Electrical and Computer Engineering from Cornell University.

Dana Vantrease specializes in hw and sw solutions for custom AI silicon. She has worked on such systems at Amazon Web Services (Inferentia, Trainium), Qualcomm (NPU), and MatX.

Sayeh Sharify received her B.Sc. degree in Computer Engineering from Sharif University of Technology in 2013, and her M.A.Sc. degree in Electrical Engineering from University of Toronto in 2015, where she is currently a third year Ph.D. student. Her research interests include computer architecture, machine learning, embedded systems, and reconfigurable computing. She is currently working on designing hardware accelerators for machine learning algorithms.