I am a PhD candidate at the University of Illinois at Urbana-Champaign. My advisor is Prof Sarita Adve. My research interests include Error-Efficient Computing, Approximate Computing, Hardware Resiliency and Software Testing. The overarching theme of my dissertation work is enabling reliable, low-cost and efficient computing by allowing controlled errors in the system. My work aims to explore such opportunities in emerging workloads and build an ecosystem to formalize and automate the application of error-efficient computing techniques. I am among the young researchers selected to participate in the 2018 Heidelberg Laureate Forum.

Before joining UIUC, I was a CPU/Silicon validation engineer at Intel for five years, where I won a divisional award for key contributions in validating new industry standard CPU features. Prior to that I worked for 1.5 years at Qualcomm on the architectural verification of the Snapdragon processor. I completed my MS in ECE from North Carolina State University. My undergraduate degree, in Electrical Engineering, is from the University of Madras in India.

Dana Vantrease specializes in hw and sw solutions for custom AI silicon. She has worked on such systems at Amazon Web Services (Inferentia, Trainium), Qualcomm (NPU), and MatX.

I am an assistant professor at the department of computer science and Engineering at AUC. Before that, I did my Ph.D. studies as a CYD doctoral fellow at EPFL. I was working with Dr. Mirjana Stojilovic at the Parallel Systems Architecture (PARSA) laboratory led by Professor Babak Falsafi.

My research interests are focused on field programmable gate arrays (FPGAs) security. In particular, I look at the possible remote attacks on FPGAs. Furthermore, I am interested in the security of heterogeneous CPU-FPGA systems. I investigate possible attacks on and across system components. The goal is to find the vulnerabilities and design lightweight and effective countermeasures.

I am grateful to have received the CYD Doctoral Fellowship, the Google Generation Scholarship, and the EPFL EDIC Fellowship.

I am Shivani Shah, completed my Bachelor of Technology majoring in Information and Communication Technology from School of Engineering and Applied Science, Ahmedabad University. Currently, I am Research Scholar at IIIT Banglore. During my graduation, I have done a few projects such as 'Implementation of 8-bit MIPS processor on FPGA' (Coding Language: Verilog, Tool: Xilinx). I did my final year project on designing ‘Reduced Hardware Hybrid Branch Predictor’ at Ahmedabad University. Control Block is one of the major parts of any computer architecture, I focused on designing hybrid hardware, a combination of 1-bit predictor and 2-bit predictor, but hardware only of 2-bit predictor which drastically optimized the hardware requirements without compromising processor speed. So right now I have done instruction-level parallelism.