Sarita V. Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign. Her primary research interest is at the hardware-software interface with work spanning computer architecture, programming languages, operating systems, and applications. Her current research is on scalable system specialization and approximate computing.

She co-developed the memory consistency models for the C++ and Java programming languages, which are based on her early work on data-race-free (DRF) models. More recently, her work questioned the conventional wisdom for memory models for heterogeneous systems and showed that DRF is a superior model even for such systems. She is also known for her contributions to cache coherence (she co-developed the simple and efficient DeNovo coherence protocol); hardware reliability (she co-developed software-driven approaches for hardware reliability in the SWAT project and the concept of lifetime reliability aware architectures and dynamic reliability management in the RAMP project); power management (she led the design of GRACE, one of the first systems to implement cross-layer energy management); exploiting instruction-level parallelism (ILP) for memory system performance (she co-authored some of the first papers on exploiting ILP for memory level parallelism); and evaluation techniques for shared-memory multiprocessors with ILP processors (she led the development of the RSIM architecture simulator).

Professor Adve was named a Woman of Vision in innovation by the Anita Borg Institute for Women in Technology in 2012, an IEEE fellow in 2012, an ACM fellow in 2010, and received the ACM SIGARCH Maurice Wilkes award in 2008. For three of the last five years (2014-18), Illinois CS has selected her students' PhD theses as one of the department's two nominations for the ACM doctoral dissertation award. She currently serves as the chair of ACM SIGARCH, on the DARPA/ISAT study group, and on the board of directors of the Computing Research Association (CRA).

She received the Ph.D. and M.S. degrees in Computer Science from the University of Wisconsin - Madison in 1993 and 1989 respectively, and the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology - Bombay in 1987.

Dr. Ghazal Tashakor is a scientific staff member affiliated with multiple institutes and universities in Germany and Spain. She obtained her Ph.D. in High-Performance Computing (HPC) and advanced simulation from the Autonomous University of Barcelona in 2019. Her ongoing research endeavors primarily focus on conducting large-scale computer simulations. Additionally, she serves as a core developer in distributed and parallel architecture patterns, ranging from grid computing to data visualization/monitoring, with a specific emphasis on Big Data and advanced hierarchical models. She collaborates with various research centers in Germany, including Fraunhofer and Jülich Supercomputer Centre.

I am an Assistant Professor and an SK Hynix Faculty Fellow at the Electrical Engineering and Computer Sciences department of University of California, Berkeley. My research interests are in the area of computer architecture, with a special focus on specialized accelerator, heterogeneous architecture, and agile VLSI design methodology. Previously, I was a Senior Research Scientist at NVIDIA Research and received my Ph.D. degree in 2016 from Harvard University.

My work has been awarded a Distinguished Artifact Award at ISCA 2023, the Best Paper Award at DAC 2021, the Best Paper Award at JSSC 2020, a Best Paper Award at MICRO 2019, Top Picks in Computer Architecture (2014), and Honorable Mentions (2019*2). My Ph.D. dissertation was nominated by Harvard for ACM Doctoral Dissertation Award. I am an SK Hynix Faculty Fellow and a recipient of an NSF CAREER Award, the 2022 IEEE TCCA Young Computer Architect Award, a Google Faculty Rising Stars Award in Systems Research, a Google Research Scholar Award, a Facebook Research Award, an Okawa Foundation Research Grant, and the inaugural Dr. Sudhakar Yalamanchili Award.

Reetu Das is an Assistant Professor at University of Michigan. Prior to this, she was a research scientist at Intel Labs, and the researcher-in-residence for the Center for Future Architectures Research. She received her PhD in Computer Science and Engineering from Pennsylvania State University, University Park. Some of her recent projects include in-memory architectures, fine-grain heterogeneous core architectures for mobile systems, and low-power scalable interconnects for kilo-core processors. Her research program has been funded by National Science Foundation, the Center for Future Architectures Research (C-FAR), Semiconductor Research Corporation and Intel Corporation. Reetu is an expert in computer architecture. She has authored over 45 papers, filed 7 patents and served on over 20 technical program committees. She has served as a track chair for Design Automation Conference for two consecutive years. Her research has been recognized by several awards. She has received outstanding research and teaching assistantship awards at Pennsylvania State University, an IEEE Top Picks award, an NSF CAREER award, CRA-W Borg Early Career Award, IEEE/ACM MICRO Hall of Fame award and was recently inducted to ISCA Hall of Fame. Her recent work on in-memory design named Compute Caches received the best Demo award in C-FAR and was selected from 50 projects from leading University research groups. She also serves as the CEO of a precision medicine start-up, Sequal Inc.