Thesis Title: LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Increasing processing demand has led to the development of chip multiprocessors which can have multiple to many cores connected with each other and with the on-chip caches. These connections are established by an on-chip packet-switched Network-on-Chip (NoC). Scaling of technology nodes increases the power dissipated by the chips leading to thermal restrictions. To control the chip thermal design power, certain components (like cores and caches) may be turned off. However, in this scenario of dark silicon, the interconnect is expected to be available.

The thesis aims to save power consumed by this always ON interconnect by replacing the power-hungry SRAM buffers in the routers with low leakage Non-Volatile Memory (NVM) based buffers. However, the major challenges with the employment of the NVMs are slower writes and weak write endurance.

The thesis proposes:
1. Methods to evenly distribute the writes across these NVM buffers in order to increase their lifetime. This is done by static and dynamic allocation of buffers to the virtual channels and their selection during packet transmission.

2. Power can also be saved by using frequency scaling of the routers and/or turning off certain buffers when the usage is less. The investigation is done for all such approaches and power savings are demonstrated.

3. Endurance can be improved and energy can be saved if we can reduce the number of writes performed on the buffers. This is achieved by proposing two compression techniques leading to reduced network traffic and improved lifetime.

All the above methods help in improving the lifetime of the NVM based NoC interconnects in the context of dark silicon.

Hoda Naghibijouybari is an Assistant Professor in the Computer Science Department at Binghamton University. She received her Ph.D. in computer science from the University of California, Riverside in 2020, working with Professor Nael Abu-Ghazaleh. Her primary research interests are in the area of computer architecture, and security. Her current research focuses on architecture support for security, microarchitectural attacks, GPU security, and heterogeneous systems. Her research has resulted in the discovery of new attacks that have been disclosed to GPU companies and received coverage from technical news outlets. Her paper on GPU security (published in CCS-2018) was selected for Top Picks in Hardware and Embedded Security in 2019.

Darya Mikhailenko is pursuing a PhD in Electrical and Computer Engineering at the University of Rochester under the supervision of Prof. Engin Ipek. Her interests cover areas of energy-efficient computer architectures, machine learning for computer vision applications, memory management, accelerators, and architecture modeling for emerging technologies. Darya worked as a research assistant at Nanoelectronics Research Laboratory (Purdue University, U.S.A.) and Bioinspired Microelectronics Systems Laboratory (Nazarbayev University, Kazakhstan) on the implementation of brain-computer architecture to actualize deep neural networks. Her recent work was dedicated to techniques to minimize data movement energy by exploiting asymmetric on- and off-chip interconnects. Currently, she researches microarchitecture level optimizations for AR/VR applications.

Darya is looking for internships in the field of AR/VR related but not limited to computer architecture and machine learning algorithms.

I am currently a senior systems engineer at Qualcomm working on mobile SoC performance analysis.

I received my PhD in 2020 from the ECE department of University of California, Santa Barbara under the guidance of Prof. Yuan Xie, and my Master's degree in 2015. I completed my undergraduate studies in the ECE department of University of Illinois at Urbana-Champaign in 2014. My PhD research explores the design space of the memory fabric in memory-centric system architectures, given the emerging memory technologies and integration trends, to identify bottlenecks and trade-offs and proposes scalable solutions.