Jing (Jane) Li is a Dugald C. Jackson Assistant Professor in the department of Electrical and Computer Engineering and Computer Science (affiliated) the University of Wisconsin – Madison. She is part of Computer Architecture @ UW-Madison and Machine Learning @ UW-Madison. She is one of the PIs in SRC JUMP center – Center for Research on Intelligent Storage and Processing-In-Memory (CRISP). She spent her early career at IBM T. J. Watson Research Center as a Research Staff Member after obtaining her PhD degree from Purdue University in 2009. She is broadly interested in the big problems in computer system across the full stack. She is also a passionate computer experimentalist and enjoy building real computer systems (both hardware and software). In particular, she has made contributions to the following “memory-centric” areas: 1) domain-specific accelerator and its interaction with emerging memories (HMC/HBM/NVM), 2) programmable in-memory computing architecture enabled by emerging nonvolatile memories (PCM/RRAM/STT RAM), 3) system support (e.g., virtualization) for accelerators (e.g., FPGA), and 4) FPGA-based full system simulation infrastructure (MEG) for memory system research. A summary of her research can be found at https://wicil.ece.wisc.edu/research/. A research vision on the importance of interaction between machine learning and computer system can be found at our white paper (co-authored with a number of great researchers in both fields).

One key differentiator of her research is that besides modeling and simulations, she put strong emphasis on real hardware demonstration through architecting, designing and testing new prototypes, both at chip level and system level. The systems that she built with her students have achieved several key milestones, including a scalable graph analytics system ranked No. 1 on the GreenGraph500 list, a deep learning system that set the world-record in performance and energy efficiency for accelerating dense convolutional neural network using FPGA. She and her research team has also taped out several new computer chips with complete system support (programming model, runtime, virtualization, API, etc.) that are built with post-CMOS nonvolatile memory technology (e.g., RRAM) integrated with silicon CMOS through monolithic 3D integration, including Liquid Silicon which won DARPA Young Faculty Award (one out of 2 in computer area and one out of 26 across all areas nationwide, the first awardee in computer engineering and computer science at UW-Madison), and Two-Dimensional Associative Processor which won NSF CAREER Award, in addition to the first fabricated in-memory processing chip for search and a variable-bit storage chip that I built at IBM which won IBM's highest technical achievement award, the IBM's CEO Milestone.

Mary Jane (Janie) Irwin is an Emerita Evan Pugh University Professor in the Department of Computer Science and Engineering at The Pennsylvania State University. She retired in July 2017. Her research and teaching interests include computer architecture, energy-aware and reliability-aware design, emerging technologies, and VLSI systems design and design automation. She is a Fellow of IEEE and ACM and a member of NAE and AAAS. Awards she has received include the 2003 IEEE/CAS VLSI Transactions Best Paper of the Year Award, the 2010 ACM Athena Lecturer Award, the 2012 Ten-Year Retrospective Most Influential ASP-DAC Paper Award, the 2015 FLP Conference 25 Year Paper Recognition, the 2017 ACM/SIGDA Pioneering Achievement Award, and the 2018 EDAA Lifetime Achievement Award. Irwin received her M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign and an Honorary Doctorate from Chalmers University, Sweden.htt

I am currently a Post-Doctoral Research Fellow at University of California, Irvine with the prestigious Fellowship Award received from the Belgian-American Educational Foundation (BAEF).

I received my PhD degree in Computer Science Engineering at Ghent University, Belgium in 2017 with a thesis on "Adaptive Routing Algorithms in Networks-on-Chip", and stayed as a Post-Doctoral Researcher at the Department of Electronics and Information Systems until Dec. 2019.

I am the recipient of the Best Paper Award at the 11th International Workshop on Network-on-Chip Architectures (NoCArc) in Oct. 2018. Moreover, I serve as the TPC member and reviewer of several international conferences and journals.

Sonal is a assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Raipur. Prior NIT Raipur, she was postdoctoral fellow at Indian Institute of Technology (IIT) Guwahati, India from March 2018-2020. She received her M.Tech and PhD degree from the Malaviya National Institute of Technology (MNIT) Jaipur, India. Her PhD dissertation was on Exploration of Efficient Manycore Multiple Networks-on-Chip Architectures. Her research interests lie in improving energy efficiency via power-gating for multiple networks-on-chip (NoC) architectures and self-learning NoC architectures. Her thesis work awarded travel grant in DATE 2019. She is the recipient of the best paper award by TCVLSI in IEEE-SES 2018. Her PhD work is published in reputed conferences VDAT 2015, VLSI Design 2016, DAC 2019 and journals. She has received multiple recognitions, including PhD Fellowship by the Ministry of Human Resource and Development (MHRD) Govt. of India and Institute Postdoctoral Fellowship by Indian Institute of Technology Guwahati.