Harini Muthukrishnan is a final year Ph.D. Candidate at the University of Michigan where she is advised by Prof. Tom Wenisch. Her research focuses on improving strong scaling in multi-GPU systems by optimizing fine-grained transfers and is in collaboration with Systems Architecture Research Group at NVIDIA Research.

I am a Ph.D. candidate at Carnegie Mellon University, advised by Prof. Onur Mutlu and Prof. Phil Gibbons. My research focuses on the interaction between programming models, system software, and hardware architecture, and explores how richer cross-layer abstractions can enhance performance, programmability, and portability. I am excited about rethinking the roles played by different levels of the stack in the modern era of rapidly evolving, specialized, and data-centric computing landscapes. During my Ph.D., I have been fortunate to intern at Microsoft Research, Nvidia Research, and Intel Labs. I am currently a visiting student at ETH Zurich.

My main research focus is in hardware accelerators, especially FPGAs. I have done research in floating point implementations, unsupervised learning, medical imaging, and privacy preserving data processing. At Northeastern I am head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering group. Throughout my career, I have been funded by both government agencies and companies, including AMD, DARPA, NSF, Google, and MathWorks. I am the recipient of a Fulbright Scholar Award and a Charter Member of the IEEE Computer Society Distinguished Contributor Recognition Program. My current research focus is on FPGAs in the data center and FPGAs directly attached to the network.

I teach computer architecture and design courses at SJSU's computer engineering department. I have 13 years of academic work experience. My research interests includes processor architectures, memory subsystems, and performance evaluations.
I earned my M.Tech. (2011) and Ph.D. (2022) degrees from Amrita Vishwa Vidyapeetham in Bangalore, India, where I worked on low-power cache architecture and fine-grain data classification in cache coherence mechanisms to improve system performance. My work has appeared in computer architecture conferences (PDP) and the JPDC journal.