PhD Student at University of Maryland, College Park, working on Emerging Technologies on Computer Architecture

I am a third-year PhD student in Electrical and Computer Engineering interested in new and niche logic families for high-performance computing purposes, including temporal-based encoding (Race Logic), and exploring superconducting architectural and circuit design trade-offs between area, energy, and tolerance to variability. I have co-authored several papers at ISCA and ASPLOS on novel logic paradigms applied to superconducting technologies. I am currently pursuing several projects, including new neuromorphic gates in superconducting electronics, and new fan-out techniques for the same technology. I have a diverse background ranging from instrumentation and testing in High-Energy Physics to embedded development in the health and wellness industry, and I received my undergraduate degree in Electrical Engineering from University of California, Santa Cruz. If you would like to hear about my research, please reach out!

Hai “Helen” Li is currently Clare Boothe Luce Associate Professor of Electrical and Computer Engineering Department at Duke University, USA. She received the B.S. and M.S. degrees from Tsinghua University, China, and the Ph.D. degree from the Department of Electrical and Computer Engineering, Purdue University, USA. Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li is a distinguished member of ACM, a distinguished speaker of ACM (2017-2020), and a distinguished lecture of IEEE CAS society (2018-2019).

Sonal is a assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Raipur. Prior NIT Raipur, she was postdoctoral fellow at Indian Institute of Technology (IIT) Guwahati, India from March 2018-2020. She received her M.Tech and PhD degree from the Malaviya National Institute of Technology (MNIT) Jaipur, India. Her PhD dissertation was on Exploration of Efficient Manycore Multiple Networks-on-Chip Architectures. Her research interests lie in improving energy efficiency via power-gating for multiple networks-on-chip (NoC) architectures and self-learning NoC architectures. Her thesis work awarded travel grant in DATE 2019. She is the recipient of the best paper award by TCVLSI in IEEE-SES 2018. Her PhD work is published in reputed conferences VDAT 2015, VLSI Design 2016, DAC 2019 and journals. She has received multiple recognitions, including PhD Fellowship by the Ministry of Human Resource and Development (MHRD) Govt. of India and Institute Postdoctoral Fellowship by Indian Institute of Technology Guwahati.