Natalie Enright Jerger is the Canada Research Chair in Computer Architecture and a Professor of Electrical and Computer Engineering at the University of Toronto. She is currently serving as the Director of the Division of Engineering Scinece at the University of Toronto. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008, respectively. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal recipient and the 2015 Borg Early Career Award winner. She served as the program co-chair of the 7th Network-on-Chip Symposium, as the program chair of the 20th International Symposium on High Performance Computer Architecture and as program co-chair for the International Conference on Architectural Support for Programming Languages and Operating Systems in 2023. She is currently serving as the ACM SIGARCH Chair. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. She is also passionate about increasing the representation of women in computing, particular in computer architecture. She is the former chair of the organizing committee for the Women in Computer Architecture group (WICARCH). In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. Her research has been supported by NSERC, Intel, CFI, AMD and Qualcomm.

Broadly speaking, I'm interested in computer architecture, particularly parallel systems. Prior work has included workload characterization of parallel applications and memory systems in traditional multiprocessor systems and GPUs and correctness in IoT systems.

I am an Assistant Professor in the Computer Science and Engineering Department at University of California, San Diego. My research spans and stretches the boundary between computer architecture and system software, with an emphasis on memory and storage systems and domain-specific acceleration. I am particularly interested in architecting emerging memory technologies (e.g., nonvolatile memories and 3D-stacked memory) into future data centers and edge computing systems that execute various applications, e.g., machine learning, big-data analytics, smart home, and smart transportation. I am also interested in developing deep learning to help computer systems design and programming.

Shaizeen is a Researcher at AMD Research. She received her M.S. and Ph.D. from the University of Michigan, Ann Arbor in 2013 and 2017, respectively. Her research interests include design of novel near-data computing solutions and techniques to reduce data movement in heterogeneous systems. She has received several awards and honors for her research including winning the best demo award at the 2016 Center for Future Architectures Research (CFAR) Annual Research Review which showcased nearly 50 projects in computer architecture related topics from several leading institutions. Her work during her undergraduate days won 1st place in Parallel Computing at Imagine Cup 2009, a worldwide student technical competition organized by Microsoft.