Aninda Manocha received her Ph.D student in Computer Science at Princeton University. She was advised by Professor Margaret Martonosi in the broad area of Computer Architecture. More specifically, she worked on the design of reconfigurable hardware to accelerate a variety of software applications with a focus on the application and compiler interface. She also worked on memory hierarchy designs and operating system techniques tailored to irregular, memory-intensive graph applications. She received her B.S. in Electrical and Computer Engineering as well as Computer Science from Duke University in 2018. She now works at Rivos.

I'm a Ph.D. candidate at Department of Computer Science and Engineering, Indian Institute of Technology, Madras, advised by Prof. Chester Rebeiro. My research interests are broadly in the area of secure systems design, with a specific focus on micro-architecture level solutions against various attacks against cryptographic implementations, such as cache side-channel attacks. I'm also interested in exploring the applications of AI to help in building a more secure framework. I was one among the 12 candidates across the world to present my research at Lenovo AI Innovation Challenge Event at SuperComputing Conference 2017, Denver, Colorado. I was also one of the three-member team from IIT Madras that won the First Place in the CSAW Embedded Security Challenge 2016. We designed a secure implementation of an OpenRISC processor to detect and prevent buffer overflow attacks.

My research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design for embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. In 2017, I have been elevated to the grade of IEEE Fellow “for contributions to energy-efficient computer architectures”. Recently I was European Project Coordinator of the H2020-FET-HPC project ANTAREX-671623 (2015-2018) on "Autotuning and adaptivity approach for energy efficient exascale HPC systems”. I was Project Coordinator of two other European projects: FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). I am an active member of the scientific community and I regularly serve in several international program committees. I annually teach basic and advanced courses on computer architectures and operating systems.

I am passionate about research and teaching. I want to gain expertise in the field of multi-core architecture and improve coherency and synchronization methods which are crucial for performance in the cutting edge computing applications. I recently gradauted and my research proposed multi-word atomics and its implementation in hardware to assist lock-free programs that are otherwise extremely difficult to program. I am currently working as a CPU architect at Google's CPU team. Additionally, I strongly believe that diversity is instrumental in finding innovative solutions and am committed to making computing a more inclusive world.