Broadly speaking, I'm interested in computer architecture, particularly parallel systems. Prior work has included workload characterization of parallel applications and memory systems in traditional multiprocessor systems and GPUs and correctness in IoT systems.

Reetu Das is an Assistant Professor at University of Michigan. Prior to this, she was a research scientist at Intel Labs, and the researcher-in-residence for the Center for Future Architectures Research. She received her PhD in Computer Science and Engineering from Pennsylvania State University, University Park. Some of her recent projects include in-memory architectures, fine-grain heterogeneous core architectures for mobile systems, and low-power scalable interconnects for kilo-core processors. Her research program has been funded by National Science Foundation, the Center for Future Architectures Research (C-FAR), Semiconductor Research Corporation and Intel Corporation. Reetu is an expert in computer architecture. She has authored over 45 papers, filed 7 patents and served on over 20 technical program committees. She has served as a track chair for Design Automation Conference for two consecutive years. Her research has been recognized by several awards. She has received outstanding research and teaching assistantship awards at Pennsylvania State University, an IEEE Top Picks award, an NSF CAREER award, CRA-W Borg Early Career Award, IEEE/ACM MICRO Hall of Fame award and was recently inducted to ISCA Hall of Fame. Her recent work on in-memory design named Compute Caches received the best Demo award in C-FAR and was selected from 50 projects from leading University research groups. She also serves as the CEO of a precision medicine start-up, Sequal Inc.

My research interests are in Computer Architecture and Systems and my current research focuses on optimizing GPU architectures for Deep Learning applications, specifically Recurrent Neural Networks. I have been a part of the effort to augment GPGPU-Sim, a widely used GPU simulator, to execute Deep Learning kernels written using NVIDIA's cuDNN and cuBLAS libraries. My research advisor is Prof. Matthew D. Sinclair.

Natalie Enright Jerger is the Canada Research Chair in Computer Architecture and a Professor of Electrical and Computer Engineering at the University of Toronto. She is currently serving as the Director of the Division of Engineering Scinece at the University of Toronto. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008, respectively. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal recipient and the 2015 Borg Early Career Award winner. She served as the program co-chair of the 7th Network-on-Chip Symposium, as the program chair of the 20th International Symposium on High Performance Computer Architecture and as program co-chair for the International Conference on Architectural Support for Programming Languages and Operating Systems in 2023. She is currently serving as the ACM SIGARCH Chair. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. She is also passionate about increasing the representation of women in computing, particular in computer architecture. She is the former chair of the organizing committee for the Women in Computer Architecture group (WICARCH). In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. Her research has been supported by NSERC, Intel, CFI, AMD and Qualcomm.