Diana Marculescu is Department Chair, Cockrell Family Chair for Engineering Leadership #5, and Professor, Motorola Regents Chair in Electrical and Computer Engineering #2, at the University of Texas at Austin.

Prior to joining UT Austin in December 2019, she was the David Edward Schramm Professor of Electrical and Computer Engineering, the Founding Director of the College of Engineering Center for Faculty Success (2015-2019) and has served as Associate Department Head for Academic Affairs in Electrical and Computer Engineering (2014-2018), all at Carnegie Mellon University.

She received the Dipl.Ing. degree in computer science from the Polytechnic University of Bucharest, Bucharest, Romania (1991), and the Ph.D. degree in computer engineering from the University of Southern California, Los Angeles, CA (1998). Her research interests include energy- and reliability-aware computing, hardware aware machine learning, and computing for sustainability and natural science applications.

Diana was a recipient of the National Science Foundation Faculty Career Award (2000-2004), the ACM SIGDA Technical Leadership Award (2003), the Carnegie Institute of Technology George Tallman Ladd Research Award (2004), and several best paper awards. She was an IEEE Circuits and Systems Society Distinguished Lecturer (2004-2005) and the Chair of the Association for Computing Machinery (ACM) Special Interest Group on Design Automation (2005-2009). Diana chaired several conferences and symposia in her area and is currently an Associate Editor for IEEE Transactions on Computers. She was selected as an ELATE Fellow (2013-2014), and is the recipient of an Australian Research Council Future Fellowship (2013-2017), the Marie R. Pistilli Women in EDA Achievement Award (2014), and the Barbara Lazarus Award from Carnegie Mellon University (2018). Diana is a Fellow of ACM and IEEE.

I am a PhD student in the School of Electrical and Computer Engineering at Purdue University. I received my Bachelors (2018) in Electronics and Communication Engineering (with honors) from Indian Institute of Technology Roorkee, India. I was a recipient of the IITR Heritage Excellence Award, INSA-NASI-IASc Summer Research Fellowship, and ENCORE Scholarship Award for outstanding performance in academics and curricular during my time at IIT Roorkee. Subsequently, I worked for Texas Instruments for one year on standard cell design and methodologies in collaboration in EDA team. I joined my PhD program in Fall 2019 and since have been a part of Nanoelectronics Research Lab. My research interests include computer architecture, hardware accelerators for Machine Learning applications using emerging technologies, and design of processing in/near memory based architectures. In my free time, I like to play badminton, dance, go for running, or listen to music.

Karin Strauss is a senior principal research manager at Microsoft (https://www.microsoft.com/en-us/research) and an affiliate full professor at the Department of Computer Science and Engineering (http://www.cs.washington.edu/) at University of Washington (http://www.washington.edu/). Her research lies at the intersection of computer architecture, systems, and biology. Her work includes hardware accelerators for machine learning, emerging memory technologies, and the use of biotechnology to the benefit of the IT industry. Lately, her focus has been on creating an end-to-end system that stores digital data in synthetic DNA, for which she was named one of the 2016 “100 Most Creative People in Business” by Fast Company. Along with Luis Ceze, she has recently received the ACM SIGARCH Maurice Wilkes Award for their work on DNA data storage. The DNA data storage project has also been chosen as “Best of What’s New” by Popular Science in 2016, one of the "Top 10 Emerging Technologies" by the World Economic Forum in 2019, and highlighted by influential publications such as the New York Times, Wall Street Journal, MIT Technology Review, and Scientific American. Karin received her PhD in Computer Science from University of Illinois at Urbana-Champaign in 2007.

Thesis Title: LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Increasing processing demand has led to the development of chip multiprocessors which can have multiple to many cores connected with each other and with the on-chip caches. These connections are established by an on-chip packet-switched Network-on-Chip (NoC). Scaling of technology nodes increases the power dissipated by the chips leading to thermal restrictions. To control the chip thermal design power, certain components (like cores and caches) may be turned off. However, in this scenario of dark silicon, the interconnect is expected to be available.

The thesis aims to save power consumed by this always ON interconnect by replacing the power-hungry SRAM buffers in the routers with low leakage Non-Volatile Memory (NVM) based buffers. However, the major challenges with the employment of the NVMs are slower writes and weak write endurance.

The thesis proposes:
1. Methods to evenly distribute the writes across these NVM buffers in order to increase their lifetime. This is done by static and dynamic allocation of buffers to the virtual channels and their selection during packet transmission.

2. Power can also be saved by using frequency scaling of the routers and/or turning off certain buffers when the usage is less. The investigation is done for all such approaches and power savings are demonstrated.

3. Endurance can be improved and energy can be saved if we can reduce the number of writes performed on the buffers. This is achieved by proposing two compression techniques leading to reduced network traffic and improved lifetime.

All the above methods help in improving the lifetime of the NVM based NoC interconnects in the context of dark silicon.