I am a PhD candidate in the Computer Science Department at Georgia Institute of Technology advised by Professor Hadi Esmaeilzadeh. I received my Bachelors (2012) in Electrical Engineering from Indian Institute of Technology Ropar, India where I was honored with the President of India Gold medal for my outstanding academic performance. Subsequently, I completed my Masters (2014) from the University of Texas, at Austin in Electrical and Computer Engineering. I joined my PhD studies in Fall 2014 and since have been a part of Alternate Computing Technologies lab. My research interests include computer architecture, microarchitecture design, and developing alternative technologies for efficient computing. I am continuously working towards designing full stack solutions and template-based architectures for accelerating Machine Learning and Deep Learning algorithms on an FPGA. Besides my primary research-area of computer architecture, I have also worked at the intersection of machine learning, hardware design, programming languages and databases. In my free time, I like to spend time oil painting, cooking, and reading novels.

My research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design for embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. In 2017, I have been elevated to the grade of IEEE Fellow “for contributions to energy-efficient computer architectures”. Recently I was European Project Coordinator of the H2020-FET-HPC project ANTAREX-671623 (2015-2018) on "Autotuning and adaptivity approach for energy efficient exascale HPC systems”. I was Project Coordinator of two other European projects: FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). I am an active member of the scientific community and I regularly serve in several international program committees. I annually teach basic and advanced courses on computer architectures and operating systems.

I am a PhD candidate in the Department of Electrical and Computer Engineering at the University of British Columbia, advised by Prof. Tor Aamodt. My Ph.D. thesis is on Energy-Efficient Acceleration for Autonomous Robotics. I have worked on algorithm-hardware co-optimization for robot perception and planning. My primary research area is Computer Architecture, and I have been focusing on building better computing platforms for deep learning and robotics tasks.

Before joining PhD, I worked in Qualcomm as a part of the VLSI Design Team. I received my master's in Microelectronics and VLSI from the Indian Institute of Technology Bombay, and I received a Silver Medal and Best Thesis Award for my academic performance and research contributions.

I am currently in the Job market and actively looking for research positions!

Sarita V. Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign. Her primary research interest is at the hardware-software interface with work spanning computer architecture, programming languages, operating systems, and applications. Her current research is on scalable system specialization and approximate computing.

She co-developed the memory consistency models for the C++ and Java programming languages, which are based on her early work on data-race-free (DRF) models. More recently, her work questioned the conventional wisdom for memory models for heterogeneous systems and showed that DRF is a superior model even for such systems. She is also known for her contributions to cache coherence (she co-developed the simple and efficient DeNovo coherence protocol); hardware reliability (she co-developed software-driven approaches for hardware reliability in the SWAT project and the concept of lifetime reliability aware architectures and dynamic reliability management in the RAMP project); power management (she led the design of GRACE, one of the first systems to implement cross-layer energy management); exploiting instruction-level parallelism (ILP) for memory system performance (she co-authored some of the first papers on exploiting ILP for memory level parallelism); and evaluation techniques for shared-memory multiprocessors with ILP processors (she led the development of the RSIM architecture simulator).

Professor Adve was named a Woman of Vision in innovation by the Anita Borg Institute for Women in Technology in 2012, an IEEE fellow in 2012, an ACM fellow in 2010, and received the ACM SIGARCH Maurice Wilkes award in 2008. For three of the last five years (2014-18), Illinois CS has selected her students' PhD theses as one of the department's two nominations for the ACM doctoral dissertation award. She currently serves as the chair of ACM SIGARCH, on the DARPA/ISAT study group, and on the board of directors of the Computing Research Association (CRA).

She received the Ph.D. and M.S. degrees in Computer Science from the University of Wisconsin - Madison in 1993 and 1989 respectively, and the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology - Bombay in 1987.