McKee received her bachelor’s degree in Computer Science from Yale University, master’s from Princeton University, and doctorate from the University of Virginia. Her dissertation advisor was Bill Wulf, with whom she worked on memory systems architecture. Together they coined the now-common term the “memory wall” to describe a situation in which processors are always waiting on memory, and CPU performance is therefore entirely limited by memory performance.

Before graduate school, McKee worked for Digital Equipment Corporation and Microsoft Corporation. She has also held internships at Digital Equipment Corporation’s Systems Research Center (now HP Labs) and the former AT&T Bell Labs. McKee worked as a Post-Doctoral Research Associate in the University of Virginia Computer Science Department for a year after graduating (waiting for the chip to come back from fab) and as a Computer Architect at Intel’s Microcomputer Research Lab in Oregon for the next two years. During her time at Intel, she also taught at the Oregon Graduate Institute and Reed College. McKee was a Research Assistant Professor at the University of Utah’s School of Computing from 1998 to 2002, where she worked on the Impulse Adaptable Memory Controller project. She joined Cornell University’s Computer Systems Lab within the School of Electrical and Computer Engineering in 2002. She moved to the Department of Computer Science and Engineering at Chalmers University of Technology in 2008, and she became the C. Tycho Howle endowed chair within the Holcombe Department of Electrical and Computer Engineering at Clemson University in 2018. She spent the 2017 calendar year on sabbatical at Rambus Labs in Sunnyvale, CA.

Her research has historically focused mainly on analyzing application memory behavior and designing more efficient memory systems together with the software to exploit them. Achieving this broad objective requires developing new underpinnings for system understanding, and thus she and her students and collaborators have developed new approaches to performance analysis; built scalable tools for application analysis and system modeling; designed architectures to enable more comprehensive system introspection and analyses; designed efficient memory systems for HPC and embedded platforms; and automated memory optimizations for HPC applications.

I am currently a Post-Doctoral Research Fellow at University of California, Irvine with the prestigious Fellowship Award received from the Belgian-American Educational Foundation (BAEF).

I received my PhD degree in Computer Science Engineering at Ghent University, Belgium in 2017 with a thesis on "Adaptive Routing Algorithms in Networks-on-Chip", and stayed as a Post-Doctoral Researcher at the Department of Electronics and Information Systems until Dec. 2019.

I am the recipient of the Best Paper Award at the 11th International Workshop on Network-on-Chip Architectures (NoCArc) in Oct. 2018. Moreover, I serve as the TPC member and reviewer of several international conferences and journals.

Thesis Title: LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Increasing processing demand has led to the development of chip multiprocessors which can have multiple to many cores connected with each other and with the on-chip caches. These connections are established by an on-chip packet-switched Network-on-Chip (NoC). Scaling of technology nodes increases the power dissipated by the chips leading to thermal restrictions. To control the chip thermal design power, certain components (like cores and caches) may be turned off. However, in this scenario of dark silicon, the interconnect is expected to be available.

The thesis aims to save power consumed by this always ON interconnect by replacing the power-hungry SRAM buffers in the routers with low leakage Non-Volatile Memory (NVM) based buffers. However, the major challenges with the employment of the NVMs are slower writes and weak write endurance.

The thesis proposes:
1. Methods to evenly distribute the writes across these NVM buffers in order to increase their lifetime. This is done by static and dynamic allocation of buffers to the virtual channels and their selection during packet transmission.

2. Power can also be saved by using frequency scaling of the routers and/or turning off certain buffers when the usage is less. The investigation is done for all such approaches and power savings are demonstrated.

3. Endurance can be improved and energy can be saved if we can reduce the number of writes performed on the buffers. This is achieved by proposing two compression techniques leading to reduced network traffic and improved lifetime.

All the above methods help in improving the lifetime of the NVM based NoC interconnects in the context of dark silicon.