My main research focus is in hardware accelerators, especially FPGAs. I have done research in floating point implementations, unsupervised learning, medical imaging, and privacy preserving data processing. At Northeastern I am head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering group. Throughout my career, I have been funded by both government agencies and companies, including AMD, DARPA, NSF, Google, and MathWorks. I am the recipient of a Fulbright Scholar Award and a Charter Member of the IEEE Computer Society Distinguished Contributor Recognition Program. My current research focus is on FPGAs in the data center and FPGAs directly attached to the network.

I am currently a Ph.D. Research Scholar with the School of IT, Indian Institute of Technology Delhi, New Delhi, India.
My current research interests span the areas of architecture design and acceleration techniques for computer vision and image processing applications, designing convolutional neural network accelerators, and machine learning applications to computer architecture.

Research interests include energy-efficient computing, hardware-software co-design, near memory processing, non-volatile memory.

I am an Assistant Professor in the Department of Computer Science at George Mason University. My research interest mainly falls in system reliability and GPU architecture, including the reliable operation of GPUs, non-conventional sensors, autonomous driving systems, and neural networks.