WICArch Directory

Ruth's focus is on the promotion of secure DevOps strategies. Over the past 20 years she has been a member of many technical panels and ISO committees including chairing the NSAI/TC 2/SC 11 on cloud and distributed systems. Ruth is a member of the working group which developed the IEEE 2675 DevOps standard. Ruth’s goal in DevOps is to ensure that security and performance are seen as core to development projects just as it is in configuration projects.

Photonic chip that utilizes neural network.

I am an Assistant Professor in the Department of Computer Science at George Mason University. My research interest mainly falls in system reliability and GPU architecture, including the reliable operation of GPUs, non-conventional sensors, autonomous driving systems, and neural networks.

I work on computer systems for large-scale applications such as cloud computing services, data analytics, and machine learning. The goal of my research is to improve the performance and resource efficiency of cloud computing while making it easier for users to deploy and manage their applications. My research interests span operating systems, computer architecture, and their intersection with machine learning.

Jing (Jane) Li is a Dugald C. Jackson Assistant Professor in the department of Electrical and Computer Engineering and Computer Science (affiliated) the University of Wisconsin – Madison. She is part of Computer Architecture @ UW-Madison and Machine Learning @ UW-Madison. She is one of the PIs in SRC JUMP center – Center for Research on Intelligent Storage and Processing-In-Memory (CRISP). She spent her early career at IBM T. J. Watson Research Center as a Research Staff Member after obtaining her PhD degree from Purdue University in 2009. She is broadly interested in the big problems in computer system across the full stack. She is also a passionate computer experimentalist and enjoy building real computer systems (both hardware and software). In particular, she has made contributions to the following “memory-centric” areas: 1) domain-specific accelerator and its interaction with emerging memories (HMC/HBM/NVM), 2) programmable in-memory computing architecture enabled by emerging nonvolatile memories (PCM/RRAM/STT RAM), 3) system support (e.g., virtualization) for accelerators (e.g., FPGA), and 4) FPGA-based full system simulation infrastructure (MEG) for memory system research. A summary of her research can be found at https://wicil.ece.wisc.edu/research/. A research vision on the importance of interaction between machine learning and computer system can be found at our white paper (co-authored with a number of great researchers in both fields).

One key differentiator of her research is that besides modeling and simulations, she put strong emphasis on real hardware demonstration through architecting, designing and testing new prototypes, both at chip level and system level. The systems that she built with her students have achieved several key milestones, including a scalable graph analytics system ranked No. 1 on the GreenGraph500 list, a deep learning system that set the world-record in performance and energy efficiency for accelerating dense convolutional neural network using FPGA. She and her research team has also taped out several new computer chips with complete system support (programming model, runtime, virtualization, API, etc.) that are built with post-CMOS nonvolatile memory technology (e.g., RRAM) integrated with silicon CMOS through monolithic 3D integration, including Liquid Silicon which won DARPA Young Faculty Award (one out of 2 in computer area and one out of 26 across all areas nationwide, the first awardee in computer engineering and computer science at UW-Madison), and Two-Dimensional Associative Processor which won NSF CAREER Award, in addition to the first fabricated in-memory processing chip for search and a variable-bit storage chip that I built at IBM which won IBM's highest technical achievement award, the IBM's CEO Milestone.

I am a PhD candidate at the University of Illinois at Urbana-Champaign. My advisor is Prof Sarita Adve. My research interests include Error-Efficient Computing, Approximate Computing, Hardware Resiliency and Software Testing. The overarching theme of my dissertation work is enabling reliable, low-cost and efficient computing by allowing controlled errors in the system. My work aims to explore such opportunities in emerging workloads and build an ecosystem to formalize and automate the application of error-efficient computing techniques. I am among the young researchers selected to participate in the 2018 Heidelberg Laureate Forum.

Before joining UIUC, I was a CPU/Silicon validation engineer at Intel for five years, where I won a divisional award for key contributions in validating new industry standard CPU features. Prior to that I worked for 1.5 years at Qualcomm on the architectural verification of the Snapdragon processor. I completed my MS in ECE from North Carolina State University. My undergraduate degree, in Electrical Engineering, is from the University of Madras in India.

I am currently a Post-Doctoral Research Fellow at University of California, Irvine with the prestigious Fellowship Award received from the Belgian-American Educational Foundation (BAEF).

I received my PhD degree in Computer Science Engineering at Ghent University, Belgium in 2017 with a thesis on "Adaptive Routing Algorithms in Networks-on-Chip", and stayed as a Post-Doctoral Researcher at the Department of Electronics and Information Systems until Dec. 2019.

I am the recipient of the Best Paper Award at the 11th International Workshop on Network-on-Chip Architectures (NoCArc) in Oct. 2018. Moreover, I serve as the TPC member and reviewer of several international conferences and journals.

Yasuko Eckert is a Sr. Member of Technical Staff at AMD Research and an IEEE Senior Member. She received her M.S. and Ph.D. from the University of Wisconsin-Madison in 2007 and 2011, respectively. She received her B.S. from the University of Texas at Austin in 2004. Her research interests include SoC- and package-level architectural optimizations, 3D integration, energy-efficient computing, and microarchitecture designs. She is currently serving as the Tutorial/Workshop Co-chair of the 51st International Symposium on Microarchitecture, as well as an Associate Editor of IEEE Transactions on Multi-Scale Computing Systems (TMSCS). She has served on the Technical Program Committees of MICRO, HPCA, PACT, ISLPED, and ICCD. She holds more than 25 U.S. patents.

Bahar Asgari is an assistant professor in the Department of Computer Science at the University of Maryland, Collage Park with a joint appointment in UMIACS. Before joining UMD in August 2022, she spent a year working at Google on its Systems and Services Infrastructure team. She received her Ph.D. in electrical and computer engineering from Georgia Tech in 2021, where she was advised by Dr. Sudhakar Yalamanchili and Dr. Hyesoon Kim. Bahar’s research interests include but are not limited to domain-specific architecture design, near memory processing, and reconfigurable computing. Her proposed low-cost hardware accelerators and hardware/software co-optimization that deal with essential challenges of sparse problems contribute to a widespread application domain from machine learning to scientific computing.

Hi, I am Xiaoxiao (Sia) Li. Now I am a postdoc in the CS department at Princeton. I am fortunate to be advised by Prof. Kai Li and Prof. Olga Troyanskaya. My current research has been focused on the interdisciplinary field of Machine Learning, Model Interpretability, Medical Data Analysis, and System Privacy. In 2020, I received my Ph.D. degree at Yale University, where I was a member of Image Processing and Analysis Group(IPAG), under the supervision of Prof. James Duncan.

I'm a Ph.D. candidate at Department of Computer Science and Engineering, Indian Institute of Technology, Madras, advised by Prof. Chester Rebeiro. My research interests are broadly in the area of secure systems design, with a specific focus on micro-architecture level solutions against various attacks against cryptographic implementations, such as cache side-channel attacks. I'm also interested in exploring the applications of AI to help in building a more secure framework. I was one among the 12 candidates across the world to present my research at Lenovo AI Innovation Challenge Event at SuperComputing Conference 2017, Denver, Colorado. I was also one of the three-member team from IIT Madras that won the First Place in the CSAW Embedded Security Challenge 2016. We designed a secure implementation of an OpenRISC processor to detect and prevent buffer overflow attacks.

I am a PhD candidate in the Department of Electrical and Computer Engineering at the University of British Columbia, advised by Prof. Tor Aamodt. My Ph.D. thesis is on Energy-Efficient Acceleration for Autonomous Robotics. I have worked on algorithm-hardware co-optimization for robot perception and planning. My primary research area is Computer Architecture, and I have been focusing on building better computing platforms for deep learning and robotics tasks.

Before joining PhD, I worked in Qualcomm as a part of the VLSI Design Team. I received my master's in Microelectronics and VLSI from the Indian Institute of Technology Bombay, and I received a Silver Medal and Best Thesis Award for my academic performance and research contributions.

I am currently in the Job market and actively looking for research positions!

I am a research scholar in the Electrical Engineering and Computer Science department at University of California, Irvine advised by Prof. Nader Bagherzadeh. I am interested lie in Accelerator based architecture, memory systems, multicore and parallel computing, and heterogeneous architectures. Currently, I am working on mitigating memory bottleneck in deep neural networks (DNN) accelerator based architectures.

McKee received her bachelor’s degree in Computer Science from Yale University, master’s from Princeton University, and doctorate from the University of Virginia. Her dissertation advisor was Bill Wulf, with whom she worked on memory systems architecture. Together they coined the now-common term the “memory wall” to describe a situation in which processors are always waiting on memory, and CPU performance is therefore entirely limited by memory performance.

Before graduate school, McKee worked for Digital Equipment Corporation and Microsoft Corporation. She has also held internships at Digital Equipment Corporation’s Systems Research Center (now HP Labs) and the former AT&T Bell Labs. McKee worked as a Post-Doctoral Research Associate in the University of Virginia Computer Science Department for a year after graduating (waiting for the chip to come back from fab) and as a Computer Architect at Intel’s Microcomputer Research Lab in Oregon for the next two years. During her time at Intel, she also taught at the Oregon Graduate Institute and Reed College. McKee was a Research Assistant Professor at the University of Utah’s School of Computing from 1998 to 2002, where she worked on the Impulse Adaptable Memory Controller project. She joined Cornell University’s Computer Systems Lab within the School of Electrical and Computer Engineering in 2002. She moved to the Department of Computer Science and Engineering at Chalmers University of Technology in 2008, and she became the C. Tycho Howle endowed chair within the Holcombe Department of Electrical and Computer Engineering at Clemson University in 2018. She spent the 2017 calendar year on sabbatical at Rambus Labs in Sunnyvale, CA.

Her research has historically focused mainly on analyzing application memory behavior and designing more efficient memory systems together with the software to exploit them. Achieving this broad objective requires developing new underpinnings for system understanding, and thus she and her students and collaborators have developed new approaches to performance analysis; built scalable tools for application analysis and system modeling; designed architectures to enable more comprehensive system introspection and analyses; designed efficient memory systems for HPC and embedded platforms; and automated memory optimizations for HPC applications.

Hi, I am Nayana, a final year Ph.D. candidate at Princeton University, advised by Prof. David August. My research interests are in the field of computer architecture and hardware/software co-design, with more focus on performance improvement at the Datacenter scale. I interned for two consecutive summers with Google Wide Profiling team at Google. Before joining Princeton, I was working as a Verification Engineer at AMD, Bangalore, India.

I am passionate about research and teaching. I want to gain expertise in the field of multi-core architecture and improve coherency and synchronization methods which are crucial for performance in the cutting edge computing applications. I recently gradauted and my research proposed multi-word atomics and its implementation in hardware to assist lock-free programs that are otherwise extremely difficult to program. I am currently working as a CPU architect at Google's CPU team. Additionally, I strongly believe that diversity is instrumental in finding innovative solutions and am committed to making computing a more inclusive world.

I'm Gelara, a forward-thinking computer architecture master's student from Iran. My focus lies in Approximate Computing, Bio-inspired Computing, and Brain Interface Computing.

Qiuyun Llull joined VMware in 2017, working on the performance of next-generation Software-defined Data Center. She is broadly interested in system and architecture for emerging applications, such as data analytics, machine learning, IoT, and autonomous driving. She received her Ph.D. in Computer Engineering from Duke University in 2017, working with Prof. Benjamin Lee. Her doctoral research applies microeconomic models to manage resources in large-scale data centers; her dissertation received Outstanding Dissertation Award from the Duke ECE department. Her recent publication (Amdahl's law in the Datacenter Era: A Market for Fair Processor Allocation) won the Best Paper Award at HPCA 2018. Before coming to the United States, she obtained her M.S. degree from University Paris Sud, France and B.Eng. degree from Huazhong University of Science and Technology, China

Computer architecture and software systems with special emphasis on multiprocessor and multicore systems, data center architectures, and large-scale distributed systems.

My research interest lies at the intersection of data, ML and system. At Meta AI, I'm exploring limits of scaling for many SOTA models.

I recently graduated from Penn State University. My research at Penn State was focused on memory and storage architecture. I worked on NAND flash solid state drives on cloud and enterprise environments. I also did an internship at Memory Solution Lab in Samsung Semiconductor where I worked on open channel solutions for SSD storage architectures. I am now a Software Engineer at Google platform team working on system drivers for cloud storages.

Computer Science Engineer, specializing in Hardware and Network Systems from SUNY Buffalo. Highly passionate about Research in the field of VLSI , Computer Architecture and Hardware Security. Also, I have a great interest in the field of Routers and Switches, MIMO technology and VLSI Digital Circuit designing. Along with my Master's I am also working as a Graduate Assistant in HPVSA Laboratory, in the Dept. of Computer Science Engineering , SUNY Buffalo. My current research is on design and optimization of Physically Unclonable Functions (PUF), which could act as a fingerprint for semiconductor devices.

Furthermore, I have obtained my Bachelor's degree in Electronics and Communication Engineering from SRMIST,Chennai,India. During my undergrad I sincerely worked under my Professor for the research project - on Tunnel Field Effect Transistor, which we presented at the National Conference Silicon'18. Our paper "Design Optimization of Tunnel Field Effect Transistor" was published in International Journal of Recent Technology and Engineering (IJRTE) in March 2019.

The amalgamation of Electronics, Computers and Communications have helped me to pave stronger base for the skills needed in the field of Computer Hardware and Computer Networks.

Tamara Silbergleit Lehman is a 5th year PhD candidate at Duke university. Her thesis work focuses on reducing overheads of secure memory. More broadly, her research interests lie on the intersection of computer architecture and security. She is also interested in memory systems, simulation methodologies and emerging technologies. Tamara has a Bachelor's degree from University of Florida in Industrial Engineering and a Masters degree in Computer Engineering from Duke University. Her latest publication on understanding metadata access patterns in secure memory at ISPASS 2018 won the best paper award. Her earlier work on developing a safe speculation mechanism for secure memory published in MICRO 2016 got an honorable mention in Micro Top Picks.

My research interests are in Computer Architecture and Systems and my current research focuses on optimizing GPU architectures for Deep Learning applications, specifically Recurrent Neural Networks. I have been a part of the effort to augment GPGPU-Sim, a widely used GPU simulator, to execute Deep Learning kernels written using NVIDIA's cuDNN and cuBLAS libraries. My research advisor is Prof. Matthew D. Sinclair.

Helena Caminal is a first-year Ph.D. student in the Computer Systems Lab at Cornell University, advised by Prof. José F. Martínez. She is generally interested in computer architecture and systems, with a focus on processing-in-memory.

Yaqi Zhang is a PhD candidate in the Electrical Engineering Department at Stanford University. Her research interest is in hardware accelerator design and compiler optimizations for spatial and parallel architectures. She received a BS in Electrical Engineering from Duke University. She is a student member of IEEE. Contact her at yaqiz@stanford.edu.

I am an Assistant Professor in the Computer Science and Engineering Department at University of California, San Diego. My research spans and stretches the boundary between computer architecture and system software, with an emphasis on memory and storage systems and domain-specific acceleration. I am particularly interested in architecting emerging memory technologies (e.g., nonvolatile memories and 3D-stacked memory) into future data centers and edge computing systems that execute various applications, e.g., machine learning, big-data analytics, smart home, and smart transportation. I am also interested in developing deep learning to help computer systems design and programming.

I am Shivani Shah, completed my Bachelor of Technology majoring in Information and Communication Technology from School of Engineering and Applied Science, Ahmedabad University. Currently, I am Research Scholar at IIIT Banglore. During my graduation, I have done a few projects such as 'Implementation of 8-bit MIPS processor on FPGA' (Coding Language: Verilog, Tool: Xilinx). I did my final year project on designing ‘Reduced Hardware Hybrid Branch Predictor’ at Ahmedabad University. Control Block is one of the major parts of any computer architecture, I focused on designing hybrid hardware, a combination of 1-bit predictor and 2-bit predictor, but hardware only of 2-bit predictor which drastically optimized the hardware requirements without compromising processor speed. So right now I have done instruction-level parallelism.

I am a Professor in the Informatics Faculty at USI Lugano, Switzerland.

I am interested in the interaction between compiler and architecture design, particularly in the field of embedded systems.

My research efforts have mostly revolved around the automation of embedded processor customization, and the definition of innovative reconfigurable fabrics --- again both in terms of how to architect them, and how to compile onto them. Recently, I have also become interested in Approximate Computing, in particular in how to approximate generic gate-level circuits automatically.

I'm Diman Zad-Tootaghaj, I am a postdoc/researcher at Hewlett Packard Labs in Palo Alto, California. I work on Software-Defined Network solutions in Wide Area Networks (SD-WAN).

I earned my PhD in Computer Science and Engineering at Pennsylvania State University. Prior to Penn State, I got my B.Sc degree in Electrical Engineering at Sharif University of Technology, Iran. During my PhD, I was working in the Institute for Networking and Security Research (INSR) and Network Sciences Research Group (NSRG) under supervision of Prof. Thomas La Porta (advisor), Dr. Ting He (co-advisor), and Dr. Novella Bartolini.

My research area is computer networks, stochastic analysis, operating system, and parallel computing. I graduated from Sharif University of technology, with MSc. in Electrical Engineering.

I'm on the N2Women board as a Website Co-chair.

Database

Interests

My main research focus is in hardware accelerators, especially FPGAs. I have done research in floating point implementations, unsupervised learning, medical imaging, and privacy preserving data processing. At Northeastern I am head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering group. Throughout my career, I have been funded by both government agencies and companies, including AMD, DARPA, NSF, Google, and MathWorks. I am the recipient of a Fulbright Scholar Award and a Charter Member of the IEEE Computer Society Distinguished Contributor Recognition Program. My current research focus is on FPGAs in the data center and FPGAs directly attached to the network.

I am a Research Scientist at IBM Research. I’m currently working on memory-centric architectures for privacy preserving applications, co-design of heterogeneous architectures and schedulers for them.

I’m currently a Product Manager at Google Cloud AI. Previously, I was the lead Product Manager for systems and software at Cerebras Systems, where we built the industry's fastest Deep Learning acceleration solution.

I have an MBA from the University of Texas-McCombs School of Business, where I was a Venture Fellow at BuildGroup and Mercury Fund; here I gained hands-on experience in developing investment themes, conducting due diligence, valuation, and assisting portfolio companies, and worked with internal data science teams to conceive and deploy machine learning projects at scale.

Prior to my MBA, I received a Masters' in Computer Engineering from the University of Wisconsin-Madison and held leadership positions within product and research groups within the smartphone industry (Qualcomm, Samsung R&D) as a computer architect.

I was fortunate to witness the explosive growth of the smartphone and tablet markets first-hand and was a member of high visibility + growth teams that collectively delivered over 1 Billion chips to users.

I am currently a Ph.D. Research Scholar with the School of IT, Indian Institute of Technology Delhi, New Delhi, India.
My current research interests span the areas of architecture design and acceleration techniques for computer vision and image processing applications, designing convolutional neural network accelerators, and machine learning applications to computer architecture.

Jun Yang is a William Kepler Whiteford Professor of Electrical and Computer Engineering Department at the University of Pittsburgh. Prior to joining the University of Pittsburgh, she was an assistant professor of the Computer Science and Engineering Department at University of California, Riverside. Jun received her bachelor from Nanjing University, China, and her PhD from the University of Arizona in 1995 and 2002 respectively. Jun’s research is in the broad area of computer architecture and her recent focuses include GPU designs, architecture level security, emerging memory technologies, 3D integration, and power and thermal management techniques. Jun is a recipient of NSF CAREER award in 2008, IEEE MICRO Top Picks award in 2010, and best paper awards of ISLPED 2013 and ICCD 2007. She was on the editorial board of IEEE Computer Architecture Letters, and she has served in the Organizing and Technical Program Committee in ISCA, MICRO, and HPCA, for many years. She has been included in the HPCA hall of fame since 2017.

Amna Shahab attended The University of Edinburgh for her doctoral studies and was advised by Boris Grot. Her research interests broadly lie in computer architecture and more specifically on memory system design for emerging datacenter workloads. She also has a passion for teaching and hopes to learn how to effectively translate it into a passion for learning from students.

I am working with heterogeneous systems, specifically with CPU, GPU and FPGA. I am investigating the behavior of a heterogeneous node, evaluating the interaction and how it can improve the execution time and energy consumption.

Antara is doing a PhD at Computer Architecture and Dependable Systems Lab (CADSL), IIT Bombay in collaboration with the University of Tokyo. She is an Intel India PhD fellow and Google WomenTechmaker Asia-Pacific scholar. She is currently interning at Microarchitecture Research Labs (MRL), Intel India. Her areas of interest include near-data processing, 3D DRAMs, convolutional neural network, non-von Neumann architecture and related topics. She has worked on multicore cache coherence protocols during her masters at IIIT Delhi. Her work on dual-port SRAMs with ST Microelectronics was published in VDAT’16. She interned at SanDisk where she designed a digital duty cycle corrector for NAND flash high-speed interface. She has also worked in automotive electronics at TATA Motors Sanand plant.

I am Wen Wang, a final-year Ph.D. student in the Department of Electrical Engineering at Yale University, working with Prof. Jakub Szefer. I am interested in post-quantum cryptography and hardware security. My research focuses on designing secure, flexible and efficient hardware/software architectures for different families of post-quantum cryptography targeting new-generation heterogeneous computing platforms.

Dr. Guo is an assistant professor in the Department of Electrical and Computer Engineering at Lehigh University. Dr. Guo received her Ph.D. degree in Electrical and Computer Engineering from the University of Rochester in 2015, and B.S. degree from Beihang University in 2009. Dr. Guo's research interests are in the broad area of computer architecture, with an emphasis on leveraging emerging technologies to build energy-efficient architectures. She received the IBM Ph.D. Fellowship twice. Dr. Guo is a recipient of the National Science Foundation CAREER Award and the Lawrence Berkeley National Laboratory Computing Sciences Research Pathways Fellowship.

Broadly speaking, I'm interested in computer architecture, particularly parallel systems. Prior work has included workload characterization of parallel applications and memory systems in traditional multiprocessor systems and GPUs and correctness in IoT systems.

Sabrina M. Neuman is an Assistant Professor of Computer Science at Boston University. Her research interests are in computer architecture design informed by explicit application-level and domain-specific insights. She is particularly focused on robotics applications because of their heavy computational demands and potential to improve the well-being of individuals in society. She received her S.B., M.Eng., and Ph.D. from MIT, and she was a postdoctoral NSF Computing Innovation Fellow at Harvard University. She is a 2021 EECS Rising Star, and her work on robotics acceleration has received Honorable Mention in IEEE Micro Top Picks 2022 and IEEE Micro Top Picks 2023. She holds the 2023-2026 Boston University Innovation Career Development Professorship.

Reetu Das is an Assistant Professor at University of Michigan. Prior to this, she was a research scientist at Intel Labs, and the researcher-in-residence for the Center for Future Architectures Research. She received her PhD in Computer Science and Engineering from Pennsylvania State University, University Park. Some of her recent projects include in-memory architectures, fine-grain heterogeneous core architectures for mobile systems, and low-power scalable interconnects for kilo-core processors. Her research program has been funded by National Science Foundation, the Center for Future Architectures Research (C-FAR), Semiconductor Research Corporation and Intel Corporation. Reetu is an expert in computer architecture. She has authored over 45 papers, filed 7 patents and served on over 20 technical program committees. She has served as a track chair for Design Automation Conference for two consecutive years. Her research has been recognized by several awards. She has received outstanding research and teaching assistantship awards at Pennsylvania State University, an IEEE Top Picks award, an NSF CAREER award, CRA-W Borg Early Career Award, IEEE/ACM MICRO Hall of Fame award and was recently inducted to ISCA Hall of Fame. Her recent work on in-memory design named Compute Caches received the best Demo award in C-FAR and was selected from 50 projects from leading University research groups. She also serves as the CEO of a precision medicine start-up, Sequal Inc.

I am currently a senior systems engineer at Qualcomm working on mobile SoC performance analysis.

I received my PhD in 2020 from the ECE department of University of California, Santa Barbara under the guidance of Prof. Yuan Xie, and my Master's degree in 2015. I completed my undergraduate studies in the ECE department of University of Illinois at Urbana-Champaign in 2014. My PhD research explores the design space of the memory fabric in memory-centric system architectures, given the emerging memory technologies and integration trends, to identify bottlenecks and trade-offs and proposes scalable solutions.

My research interests are centered around Computer Systems. I am currently focusing on storage and persistent memory technologies, with an emphasis on their impact on the way we manage large-scale data for emerging workloads in Data Science and the Internet of Things.

I completed my PhD in Computer Science at EPFL/the University of Sydney in 2020, advised by Prof. Willy Zwaenepoel. My dissertation research was on the design and implementation of efficient key-value stores for future hardware and performance requirements.

Hyeran Jeon is an Assistant Professor at the University of California Merced. Her research interests lie in energy-efficient high-throughput processor and systems design. She earned her Ph.D. at the University of Southern California in 2015. She spent her summer at IBM T.J. Watson Research Center and the fall at AMD Research as a research intern in 2012. Before pursuing her Ph.D., she worked as a systems software engineer at Samsung Electronics, Korea from 2002 to 2009. Hyeran obtained her M.S. from Georgia Institute of Technology and Korea University in 2008, and B.S. from Pusan National University, Korea in 2002.

I'm a doctoral student at the Chalmers University of Technology advised by Prof. Ioannis Sourdis. Formerly, I was a Researcher advised by Prof. Onur Mutlu at ETH Zürich, and Research Assistant to Prof. Trevor E. Carlson at the National University of Singapore. I obtained my engineering master's and bachelor's degrees in 2015 and 2013 respectively from BITS Pilani.

My recent work focuses on exploring near-data computing in the context of GPGPUs and 3D-DRAM architectures. Previously, I have worked on designing and building simulation infrastructures, energy-efficient cache memory architectures, and cache coherence protocols.

I am a faculty at Penn State Behrend where I teach Computer Architecture and Programming with C++/MATLAB. I am interested in optimizing current architecture for emerging technologies such as artificial intelligence and deep learning.

Shaizeen is a Researcher at AMD Research. She received her M.S. and Ph.D. from the University of Michigan, Ann Arbor in 2013 and 2017, respectively. Her research interests include design of novel near-data computing solutions and techniques to reduce data movement in heterogeneous systems. She has received several awards and honors for her research including winning the best demo award at the 2016 Center for Future Architectures Research (CFAR) Annual Research Review which showcased nearly 50 projects in computer architecture related topics from several leading institutions. Her work during her undergraduate days won 1st place in Parallel Computing at Imagine Cup 2009, a worldwide student technical competition organized by Microsoft.

Shuang Chen is a third-year Ph.D. student in the Computer Systems Lab at Cornell University, advised by Prof. José F. Martínez and Prof. Christina Delimitrou. She is generally interested in computer architecture and systems, with a focus on datacenters and architectural support for emerging memory technologies.

Samira Khan is an assistant professor at the University of Virginia. Her research focuses on Computer Architecture and Computer systems, especially building new systems by rethinking the traditional abstractions and redesigning system layers to adopt new technologies and enable future applications. Her group, Shiftlab thrives for "Paradigm Shift", and named after Thomas Kuhn's famous book "The Structure of Scientific Revolutions".

Akanksha Jain received her PhD in Computer Science from The University of Texas at Austin in December 2016 and is currently a Researcher at Arm Research. Her research interests are in computer architecture, with a particular focus on the memory system and on using machine learning techniques to improve the design of memory system optimizations. Her work has been recognized with a Best Paper Nomination at MICRO 2013, a Top Picks Honorable Mention at ISCA 2016, and the first place award at the Cache Replacement Championship in 2017.

Dr. Swapnita Srivastava is a highly accomplished researcher and educator in the field of computer science and engineering. With a Ph.D. in Cache Memory from Madan Mohan Malaviya University of Technology, Gorakhpur, she has made significant contributions to optimizing cache replacement policies using machine learning techniques. Her expertise extends to teaching and she has served as an Assistant Professor at prestigious institutions such as G L Bajaj Institute of Technology and Management and Galgotias University. Her research prowess is evidenced by her extensive publication record, including articles in renowned journals and presentations at international conferences. She is also a patent holder and has actively participated in faculty development programs and workshops. With a strong foundation in technical skills and a passion for research, she continues to make valuable contributions to the field of computer science.

I teach computer architecture and design courses at SJSU's computer engineering department. I have 13 years of academic work experience. My research interests includes processor architectures, memory subsystems, and performance evaluations.
I earned my M.Tech. (2011) and Ph.D. (2022) degrees from Amrita Vishwa Vidyapeetham in Bangalore, India, where I worked on low-power cache architecture and fine-grain data classification in cache coherence mechanisms to improve system performance. My work has appeared in computer architecture conferences (PDP) and the JPDC journal.

Christina is an assistant professor in the Electrical and Computer Engineering Department at Cornell and the John and Norma Balen Sesquicentennial Faculty Fellow. At Cornell she leads the SAIL group, and is also a member of the Computer Systems Laboratory (CSL). Christina works in computer architecture and computer systems, and more specifically on improving the predictability, resource efficiency, and security of large-scale datacenters.

She is the recipient of a Facebook Faculty Research Award (2017), a VMWare Research Award (2018), 3 IEEE Micro Top Picks awards (2014, 2017, 2018), a Facebook Graduate Fellowship (2014), and a Stanford Graduate Fellowship (2010-2013). Before joining Cornell, Christina received her PhD from Stanford University. She had previously received an MS also from Stanford, and a diploma in Electrical and Computer Engineering from the National Technical University of Athens.

Sayeh Sharify received her B.Sc. degree in Computer Engineering from Sharif University of Technology in 2013, and her M.A.Sc. degree in Electrical Engineering from University of Toronto in 2015, where she is currently a third year Ph.D. student. Her research interests include computer architecture, machine learning, embedded systems, and reconfigurable computing. She is currently working on designing hardware accelerators for machine learning algorithms.

I am a 2nd year PhD. student in the Department of Computer Science and Engineering at University at Buffalo. I am working under Dr. Ramalingam Sridhar. My research aims at improving the performance and energy efficiency of systems used for data intensive Machine Learning applications.

Server memory management is an evolving and challenging area. With growing memory capacity installed per machine and increasing memory DIMM costs, data center planners are facing with huge increase in memory TCO. A plausible direction is to categorize memory accesses by required service level objective (SLO) with the end goal to map lower SLO request to cheaper but low quality memory resource, while using expensive, highest quality memory resource for most critical application request. I work in Linux server memory management to categorize memory access transparent to the user space.

Rujia Wang joined Illinois Institute of Technology in Fall 2018. She earned her Ph.D. and M.S degree from Electrical and Computer Engineering Department at the University of Pittsburgh and her B.E. from Zhejiang University. Her research experience spans across multiple areas in computer engineering, including novel memory architecture, secure computing architecture, system reliability, and high-performance computing, and her work has been published in top conferences in computer architecture area.

I am a PhD candidate in the Department of Computer Science & Engineering at the University of California, Riverside. I work with Distinguished Prof. Laxmi Narayan Bhuyan and Prof.Daniel Wong and am a member of SoCal Lab at UCR. My interest lies in Computer Architecture , GPGPU Architecture design, High Performance Computing, Fault-Tolerance systems. I have worked on multiple projects on Data- Dependent Applications on GPGPU, Low power Design of GPGPU Execution units and have achieved notable improvements in terms of Performance gain and Power and Area saving.

Dana Vantrease specializes in hw and sw solutions for custom AI silicon. She has worked on such systems at Amazon Web Services (Inferentia, Trainium), Qualcomm (NPU), and MatX.

I am an Assistant Professor and an SK Hynix Faculty Fellow at the Electrical Engineering and Computer Sciences department of University of California, Berkeley. My research interests are in the area of computer architecture, with a special focus on specialized accelerator, heterogeneous architecture, and agile VLSI design methodology. Previously, I was a Senior Research Scientist at NVIDIA Research and received my Ph.D. degree in 2016 from Harvard University.

My work has been awarded a Distinguished Artifact Award at ISCA 2023, the Best Paper Award at DAC 2021, the Best Paper Award at JSSC 2020, a Best Paper Award at MICRO 2019, Top Picks in Computer Architecture (2014), and Honorable Mentions (2019*2). My Ph.D. dissertation was nominated by Harvard for ACM Doctoral Dissertation Award. I am an SK Hynix Faculty Fellow and a recipient of an NSF CAREER Award, the 2022 IEEE TCCA Young Computer Architect Award, a Google Faculty Rising Stars Award in Systems Research, a Google Research Scholar Award, a Facebook Research Award, an Okawa Foundation Research Grant, and the inaugural Dr. Sudhakar Yalamanchili Award.

Alexandra Jimborean received the PhD degree from the University of Strasbourg, France in 2012. She is assistant professor with Uppsala University since 2015. She was awarded the Anita Borg Memorial Scholarship offered by Google in recognition of excellent research, along with other 25 distinctions, awards and grants. Her research focuses on compile-time and run-time code analysis and optimization for performance and energy efficiency and on software-hardware co-designs.

Vijayalakshmi Saravanan received her Ph.D. in Computer Science and Engineering from VIT University, India under Erasmus Mundus Fellowship (EURECA) as research exchange student at Mälardalen University, Sweden and visiting researcher at Ryerson University, Canada. She is currently an Assistant Professor in Practice at University of Texas, San Antonio (UTSA) in the department of Computer Science. Prior to this, she was a Postdoctoral Associate at UB (University at Buffalo), The State University of New York, USA and University of Waterloo, Canada under the prestigious “Schlumberger Faculty for the Future” Fellowship award (2015-2017). She is having 10 years of teaching experience in two premier Universities VIT and Amrita Vishwa Vidyapeetham, India. Dr. Saravanan has published many technical articles in scholarly international journal and conferences. She is serving as technical reviewer and program committee member for reputed conference & journals such as GHC, SIGCSE and Springer. Her research interests include Power-Aware Processor Design, Big Data, IoT and Computer Architecture. She is a Senior Member of IEEE & ACM, CSI, Ex-Chair for IEEE-WIE VIT affinity group, India (2009-2015), NPA (National Postdoctoral Association) Annual Meetings committee, Workshop/IIA Co-Chair (2017-2018) Poster committee Co-chair (2018-2019) and a Board member of N2WOMEN (Networking Networking Women).

Angeles G. Navarro received her PhD in Computer Science from the University of Malaga (Spain) in 2000. She is a Professor in the Department of Computer Architecture at the University of Malaga. She has been a Research Visiting Scholar in the University of Illinois at Urbana-Champaign, the Technical University of Munich, the EPCC at the University of Edinburgh, the University of Bristol, and a Research Visitor in IBM T.J. Watson Research Center at New York and in Cray Inc at Seattle. She is the author or co-author of more than 80 papers and has served as a program committee member for several High Performance Computing related conferences. Her research interests are in parallel programming models and compilation techniques for heterogeneous and reconfigurable architectures.

Dr. Navarro has been involved in many initiatives to promote women in Computer Science. She is the co-founder of WSARTECO (Women in SARTECO), a community that is part of the Spanish Computer Architecture Scientific Society, which encourages junior and senior women working in the area to increase visibility and to develop a supporting network.

I am a PhD student in the School of Electrical and Computer Engineering at Purdue University. I received my Bachelors (2018) in Electronics and Communication Engineering (with honors) from Indian Institute of Technology Roorkee, India. I was a recipient of the IITR Heritage Excellence Award, INSA-NASI-IASc Summer Research Fellowship, and ENCORE Scholarship Award for outstanding performance in academics and curricular during my time at IIT Roorkee. Subsequently, I worked for Texas Instruments for one year on standard cell design and methodologies in collaboration in EDA team. I joined my PhD program in Fall 2019 and since have been a part of Nanoelectronics Research Lab. My research interests include computer architecture, hardware accelerators for Machine Learning applications using emerging technologies, and design of processing in/near memory based architectures. In my free time, I like to play badminton, dance, go for running, or listen to music.

I'm broadly interested in computer architecture, particularly memory systems and the management and synchronization of data. I like building whole, balanced systems and understanding how all the pieces are connected, related, and affect each other.

For decades, Moore’s Law and its partner Dennard Scaling have driven technology trends that have enabled exponential performance improvements in computer systems at manageable power dissipation. With the slowing of Moore/Dennard improvements, designers have turned to a range of approaches for extending scaling of computer systems performance and power efficiency. Unfortunately, these scaling gains come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability. My work explores the way forward for computer systems designers in this “Post-ISA” era of shifting abstractions. My group looks hardware and software design issues for specialization/heterogeneity and methods for formal verification. We are also increasingly focused on the hardware/software systems issues of Quantum Computing.

My research has focused on power and energy in large-scale computing: modeling, measurement, management, and design at the system level. I'm currently Chair of CS at Sonoma State University, a campus of the California State University system. Ph.D. students who are interested in teaching at undergraduate institutions are welcome to contact me!

I am an incoming Assistant Professor in the ECE department of Princeton University. Currently, I am a Postdoctoral Research Scholar at Stanford Medicine with Prof. Euan Ashley. I completed my Ph.D. in the Electrical Engineering department at Stanford University where I was advised by Prof. Mark Horowitz. I conduct research at the intersection of computer architecture and systems, and, computational genomics for clinical and evolutionary applications.

Previously, I received a Dual Degree (B. Tech. and M. Tech.) in Electrical Engineering from the Indian Institute of Technology, Bombay in 2017 along with the Akshay Dhoke Memorial Award.

I am a trained classical dancer with a Master's in Dance in Bharat Natyam from the Art Society, Mumbai.

Sonal is a assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Raipur. Prior NIT Raipur, she was postdoctoral fellow at Indian Institute of Technology (IIT) Guwahati, India from March 2018-2020. She received her M.Tech and PhD degree from the Malaviya National Institute of Technology (MNIT) Jaipur, India. Her PhD dissertation was on Exploration of Efficient Manycore Multiple Networks-on-Chip Architectures. Her research interests lie in improving energy efficiency via power-gating for multiple networks-on-chip (NoC) architectures and self-learning NoC architectures. Her thesis work awarded travel grant in DATE 2019. She is the recipient of the best paper award by TCVLSI in IEEE-SES 2018. Her PhD work is published in reputed conferences VDAT 2015, VLSI Design 2016, DAC 2019 and journals. She has received multiple recognitions, including PhD Fellowship by the Ministry of Human Resource and Development (MHRD) Govt. of India and Institute Postdoctoral Fellowship by Indian Institute of Technology Guwahati.

Dr. Ghazal Tashakor is a scientific staff member affiliated with multiple institutes and universities in Germany and Spain. She obtained her Ph.D. in High-Performance Computing (HPC) and advanced simulation from the Autonomous University of Barcelona in 2019. Her ongoing research endeavors primarily focus on conducting large-scale computer simulations. Additionally, she serves as a core developer in distributed and parallel architecture patterns, ranging from grid computing to data visualization/monitoring, with a specific emphasis on Big Data and advanced hierarchical models. She collaborates with various research centers in Germany, including Fraunhofer and Jülich Supercomputer Centre.

Evey Liu recently finished her undergraduate study at the University of Waterloo for Computer Engineering. She will begin graduate school at the University of Toronto with supervisor Natalie Enright Jerger in January 2019. She is passionate about generic computer architecture and is open to explore different specializations within the field.

Noa Zilberman is an Associate Professor at the University of Oxford Engineering Science Department, where she leads the Computing Infrastructure Group. Her research focuses on scalable, sustainable and resilient computing infrastructure, combining aspects of computer networks, computer architecture, reconfigurable hardware and systems.

Lizy Kurian John is B. N. Gafford Professor in the Electrical and Computer Engineering at UT Austin. She received her Ph. D in Computer Engineering from the Pennsylvania State University. Her research interests include workload characterization, performance evaluation, architectures with emerging memory technologies such as die-stacked DRAM, and high performance processor architectures for emerging workloads. She is recipient of NSF CAREER award, UT Austin Engineering Foundation Faculty Award, Halliburton, Brown and Root Engineering Foundation Young Faculty Award 2001, University of Texas Alumni Association (Texas Exes) Teaching Award 2004, The Pennsylvania State University Outstanding Engineering Alumnus 2011, etc. She has coauthored a book on Digital Systems Design using VHDL (Cengage Publishers, 2007, 2017), a book on Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She is in ISCA and HPCA Hall of Fame, holds 10 US patents and is a Fellow of IEEE.

Vivienne Sze is an Associate Professor at MIT in the Electrical Engineering and Computer Science Department. Her research interests include energy-aware signal processing algorithms, and low-power circuit and system design for portable multimedia applications, including computer vision, deep learning, autonomous navigation, and video coding. Prior to joining MIT, she was a Member of Technical Staff in the R&D Center at TI, where she designed low-power algorithms and architectures for video coding. She also represented TI in the JCT-VC committee during the development of High Efficiency Video Coding (HEVC), which received a Primetime Emmy Engineering Award. She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer, 2014).

Prof. Sze is a recipient or co-recipient of the 2011 Jin-Au Kong Outstanding Doctoral Thesis Prize in Electrical Engineering at MIT, the 2017 CICC Outstanding Invited Paper Award, the 2017 Qualcomm Faculty Award, the 2016 IEEE Micro Top Picks Award, the 2016 Google Faculty Research Award, the 2016 AFOSR Young Investigator Award, the 2016 3M Non-Tenured Faculty Award, the 2014 DARPA Young Faculty Award, the 2008 A-SSCC Outstanding Design Award and the 2007 DAC/ISSCC Student Design Contest Award.

I am a third-year PhD student in Electrical and Computer Engineering interested in new and niche logic families for high-performance computing purposes, including temporal-based encoding (Race Logic), and exploring superconducting architectural and circuit design trade-offs between area, energy, and tolerance to variability. I have co-authored several papers at ISCA and ASPLOS on novel logic paradigms applied to superconducting technologies. I am currently pursuing several projects, including new neuromorphic gates in superconducting electronics, and new fan-out techniques for the same technology. I have a diverse background ranging from instrumentation and testing in High-Energy Physics to embedded development in the health and wellness industry, and I received my undergraduate degree in Electrical Engineering from University of California, Santa Cruz. If you would like to hear about my research, please reach out!

Hoda Naghibijouybari is an Assistant Professor in the Computer Science Department at Binghamton University. She received her Ph.D. in computer science from the University of California, Riverside in 2020, working with Professor Nael Abu-Ghazaleh. Her primary research interests are in the area of computer architecture, and security. Her current research focuses on architecture support for security, microarchitectural attacks, GPU security, and heterogeneous systems. Her research has resulted in the discovery of new attacks that have been disclosed to GPU companies and received coverage from technical news outlets. Her paper on GPU security (published in CCS-2018) was selected for Top Picks in Hardware and Embedded Security in 2019.

I am a Ph.D. candidate at Carnegie Mellon University, advised by Prof. Onur Mutlu and Prof. Phil Gibbons. My research focuses on the interaction between programming models, system software, and hardware architecture, and explores how richer cross-layer abstractions can enhance performance, programmability, and portability. I am excited about rethinking the roles played by different levels of the stack in the modern era of rapidly evolving, specialized, and data-centric computing landscapes. During my Ph.D., I have been fortunate to intern at Microsoft Research, Nvidia Research, and Intel Labs. I am currently a visiting student at ETH Zurich.

I am a Postdoc researcher at ETH Zurich, working with Prof. Onur Mutlu. My research interests include non-volatile memory, processing in memory, memory security, and machine learning.

Peh Li Shiuan joins NUS as Provost’s Chair Professor in the Department of Computer Science, with a courtesy appointment in the Department of Electrical and Computer Engineering in September 2016. Previously, she was Professor of Electrical Engineering and Computer Science at MIT and was on the faculty of MIT since 2009. She was also the Associate Director for Outreach of the Singapore-MIT Alliance of Research & Technology (SMART). Prior to MIT, she was on the faculty of Princeton University from 2002. She graduated with a Ph.D. in Computer Science from Stanford University in 2001, and a B.S. in Computer Science from the National University of Singapore in 1995. Her research focuses on networked computing, in many-core chips as well as mobile wireless systems. She was awarded the IEEE Fellow in 2017, NRF Returning Singaporean Scientist Award in 2016, ACM Distinguished Scientist Award in 2011, MICRO Hall of Fame in 2011, CRA Anita Borg Early Career Award in 2007, Sloan Research Fellowship in 2006, and the NSF CAREER award in 2003.

Mary Jane (Janie) Irwin is an Emerita Evan Pugh University Professor in the Department of Computer Science and Engineering at The Pennsylvania State University. She retired in July 2017. Her research and teaching interests include computer architecture, energy-aware and reliability-aware design, emerging technologies, and VLSI systems design and design automation. She is a Fellow of IEEE and ACM and a member of NAE and AAAS. Awards she has received include the 2003 IEEE/CAS VLSI Transactions Best Paper of the Year Award, the 2010 ACM Athena Lecturer Award, the 2012 Ten-Year Retrospective Most Influential ASP-DAC Paper Award, the 2015 FLP Conference 25 Year Paper Recognition, the 2017 ACM/SIGDA Pioneering Achievement Award, and the 2018 EDAA Lifetime Achievement Award. Irwin received her M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign and an Honorary Doctorate from Chalmers University, Sweden.htt

I am an assistant professor at the department of computer science and Engineering at AUC. Before that, I did my Ph.D. studies as a CYD doctoral fellow at EPFL. I was working with Dr. Mirjana Stojilovic at the Parallel Systems Architecture (PARSA) laboratory led by Professor Babak Falsafi.

My research interests are focused on field programmable gate arrays (FPGAs) security. In particular, I look at the possible remote attacks on FPGAs. Furthermore, I am interested in the security of heterogeneous CPU-FPGA systems. I investigate possible attacks on and across system components. The goal is to find the vulnerabilities and design lightweight and effective countermeasures.

I am grateful to have received the CYD Doctoral Fellowship, the Google Generation Scholarship, and the EPFL EDIC Fellowship.

I work as a performance architect in the CPU design team at Apple. Prior to joining Apple, I have completed my PhD in computer architecture from University of Texas at Austin. My research interests include computer architecture and benchmarking, hardware/software co-design, machine learning accelerators.

Martha Kim is an Associate Professor of Computer Science at Columbia University where she leads the ARCADE Lab. Kim's research interests are in computer architecture, parallel programming, compilers, and low-power computing. Her work has explored low-cost chip manufacturing systems, reconfigurable communication networks, and fine-grained parallel application profiling techniques. Her current research focuses on hardware and software techniques to improve the usability of hardware accelerators as well as data-centric accelerator design. Kim holds a PhD in Computer Science and Engineering from the University of Washington and a bachelors in Computer Science from Harvard University. She is the recipient of the 2013 Rodriguez Family Award, the 2015 Edward and Carole Kim Faculty Involvement Award, a 2013 NSF CAREER award, and the 2016 Anita Borg Early Career Award.

My PhD work at Indian Institute of Technology Madras, was on Shared Cache Management. I am interested in architectures for emerging technologies, heterogeneous architectures and application specific accelerators.

I am broadly interested in designing efficient computer systems, and more recently, in designing energy-efficient processor and memory abstractions for datacenters.

Research interests include energy-efficient computing, hardware-software co-design, near memory processing, non-volatile memory.

I am an Assistant Professor in Computer Science and Engineering at Arizona State University (ASU). I am also the Associate Director of the NSF I/UCRC Center for Embedded Systems (CES). Before joining ASU, I held a number of industrial internship positions with Intel, IBM, and Google. I am a senior member of both ACM and IEEE.

My research area lies in Computer and System Architectures. In particular, my research interests include high-performance and energy-efficient computer architectures through

• hardware heterogeneity,
• energy harvesting techniques for emerging computing devices,
• temperature and energy management for portable electronics,
• performance characterization, analysis and prediction, and
• memory subsystem designs.

I am the recipient of the 2017 NSF CAREER Award, the 2017 IEEE Young Engineer of the Year Award, the 2014 IEEEE Best of Computer Architecture Letter Award, the 2013 Science Foundation of Arizona Bisgrove Early Career Award, and the 2011-12 Intel Ph.D. Fellowship Award. My research has been supported by both industry sources and the National Science Foundation to a level over $1.8 million.

I serve on the Executive Committee of the IEEE Technical Committee on Computer Architecture from 2017-19 and am the Program Chair for the IEEE International Symposium on Workload Characterization, 2018. I completed my M.A. and Ph.D. degrees in Electrical Engineering from Princeton University in 2008 and 2012, respectively, and received a B.Sc. degree in Electrical and Computer Engineering from Cornell University.

Charu Kalra is a PhD student in the Computer Engineering Department at Northeastern University. She is part of the Northeastern University Computer Architecture Research (NUCAR) group under the direction of Prof. David Kaeli. Her research interests include GPU compilers, software reliability, machine learning, workload characterization, and performance evaluation of GPU systems. Her PhD thesis focuses on design and evaluation of compiler-based techniques to predict and improve reliability of GPU applications. In 2014, Charu was featured on NVIDIA's 'Women Who CUDA' list. She has also pursued internships at AMD and AMD Research in the past.

I am broadly interested in hardware security. I am working on designs of new Physically Unclonable Functions (PUFs), leveraging physical properties of hardware for new cryptographic and security applications, and security verification of processor architectures.

Lillie's general research interests are in specialized hardware and software-hardware co-design, and her current work focuses on enabling efficient deep learning. She received her B.A. in Physics and Computer Science from Colgate University in 2016, and she is currently pursuing her PhD in Computer Science at Harvard University, where she works with David Brooks and Gu-Yeon Wei.

Hi! I am a 3rd year PhD student in the Computer Science department at Brown University, co-advised by professors Iris Bahar and Maurice Herlihy.

My research interests are at the intersection of computer architecture and concurrent computing. I am particularly interested in the hardware-software co-design of concurrent data structures and algorithms with emerging memory technologies, such as compute-capable memory or non-volatile memory.

My research interests lie in field-programmable technology and electronic design automation, with increasing focus on the hardware security vulnerabilities of today’s heterogeneous and intelligent computing systems.

I am a fifth-year PhD student in electrical engineering at Stanford advised by Mark Horowitz. I received my B.S. in Electrical Engineering and Business, Economics, and Management from Caltech in 2019 and my M.S. in Electrical Engineering from Stanford in 2021. My research is supported by the Quad Fellowship (2023 to 2024) and Stanford's Knight-Hennessy Graduate Fellowship (2019 to 2022).

I am broadly interested in hardware design for cryptography and machine learning applications. I am curious about the security implications of enabling faster execution of cryptographic protocols and worked on designing a fast extended GCD algorithm and accelerator for constant-time modular inversion and verifiable delay functions. On the machine learning side, I am working on dynamically adapting the execution of state-of-the-art models for use in real-time systems and am working on accelerating dynamic transformer models for computer vision in an ongoing collaboration with NVIDIA. I previously worked on building a flexible memory generator as part of an agile software-hardware co-design flow with Stanford's Agile Hardware (AHA) Project. As part of my research, I have worked on taping out chips in SKY130nm, TSMC16nm, and GF12nm. During the summer, I have interned with Meta Reality Labs, NVIDIA's Architecture Research Group, Apple, Microsoft, and Intel.

My research interest lies in the areas of computer architecture and hardware security, with a focus on defenses against transient execution attacks and cache-based side channel attacks.

Anne Bracy is a Senior Lecturer in Computer Science at Cornell University. Prior to teaching at Cornell, Dr. Bracy was a Principal Lecturer and Coordinator of Undergraduate Research in Computer Science at Washington University in St Louis. She was also a Research Scientist at the Microarchitecture Research Lab at Intel in Santa Clara, California.

Dr Bracy received her PhD from University of Pennsylvania for her work on instruction fusion under the supervision of Amir Roth. Prior to her doctoral studies she was a student at Stanford University, where she was inducted into the Phi Beta Kappa honor society.

I joined the faculty at the Colorado School of Mines in January 2022 and serve as Department Head of Computer Science. Before joining Mines, I was on the faculty at Brown University for 26 years and held dual appointments as Professor of Engineering and Professor of Computer Science. My research interests focus on energy-efficient and reliable computing, from the system level to device level. Most recently this includes the design of robotics systems.

I am a 4th year PhD student at UNC Chapel Hill, dabbling in hardware security research. I am fortunate to be advised by Prof. Cynthia Sturton.

I am broadly interested in all aspects of hardware security. The goals of my research are to help hardware designers efficiently build more secure processors that can withstand a wide range of attack programs in the field, as well as to provide interesting insights about hardware vulnerabilities to the community.

I completed my BS in Microelectronics from Peking University, and my MS in Electrical Engineering from Columbia University.

I am a Masters student under the supervision of Prof. Natalie Enright Jerger at the University of Toronto. My research interests include intermittent computing, on-chip power management, and ISAs. I have had previous industry experience at AMD, Intel PSG, and Nvidia.

Elaheh Sadredini is an assistant professor at the Department of Computer Science and Engineering at UC Riverside. She received her Ph.D. in Computer Science at the University of Virginia in 2019, advised by Professor Kevin Skadron, and she was a member at the Center for Research on Intelligent Storage and Processing in Memory (CRISP). Her research focus is on developing specialized, near-memory, and in-memory hardware accelerators for big data applications, including natural language processing, data mining, and bioinformatics. Her research has resulted in several publications at top-tier venues (such as MICRO, ASPLOS, HPCA, ICS, and KDD) and several patents and patent applications. Elaheh is the recipient of several awards, including the John A. Stankovic Graduate Research Award from the UVA Department of Computer Science for outstanding research in 2019 and the UVA International Students Office Graduation Award for Academic Excellence in 2019. She also received the best paper awards at the ACM International Conference on Computing Frontiers in 2016, the “Best of CAL” award in 2019, and a nomination for the best paper award at IISWC’19, FCCM’20, and HPCA’20.

I'm a Ph.D. student at UT Austin working with Dr. Calvin Lin. Broadly, I'm interested in microarchitectural prediction for memory systems performance and in rethinking the hardware/software interface in light of modern performance, programmability, and security challenges. I'm also interested in computer architecture education. Before coming to UT, I was a CS and EE lecturer at Texas State University, and early in my career I was a hardware verification engineer at Arm.

I am a passionate Computer Science graduate student at CSU Northridge. My research interests revolve around optimizing Phase Change Memory (PCM) for commercial use, with a focus on enhancing speed, endurance, and scalability. Concurrently, I am engaged in exploring the application of Artificial Intelligence (AI) and Machine Learning (ML) techniques to address challenges within PCM. Additionally, my curiosity extends to the broader landscape of computer architecture, aiming to contribute innovative insights that advance modern computation and communication architectures.

Karin Strauss is a senior principal research manager at Microsoft (https://www.microsoft.com/en-us/research) and an affiliate full professor at the Department of Computer Science and Engineering (http://www.cs.washington.edu/) at University of Washington (http://www.washington.edu/). Her research lies at the intersection of computer architecture, systems, and biology. Her work includes hardware accelerators for machine learning, emerging memory technologies, and the use of biotechnology to the benefit of the IT industry. Lately, her focus has been on creating an end-to-end system that stores digital data in synthetic DNA, for which she was named one of the 2016 “100 Most Creative People in Business” by Fast Company. Along with Luis Ceze, she has recently received the ACM SIGARCH Maurice Wilkes Award for their work on DNA data storage. The DNA data storage project has also been chosen as “Best of What’s New” by Popular Science in 2016, one of the "Top 10 Emerging Technologies" by the World Economic Forum in 2019, and highlighted by influential publications such as the New York Times, Wall Street Journal, MIT Technology Review, and Scientific American. Karin received her PhD in Computer Science from University of Illinois at Urbana-Champaign in 2007.

Since 2014, I am an Associate Professor at the Education and Research Department of Computer Science and Electrical Engineering in University of Rennes 1, whereas my research activities are taking place at the IRISA/INRIA Rennes Bretagne Atlantique research center. My research interests include Embedded Systems, Real-time Systems, Mixed-Critical Systems, Hardware/Software Co-design, Mapping Methodologies, Design Space Exploration Methodologies, Memory Management Methodologies, Low Power Design, Fault Tolerance.

I am a PhD Student at Chalmers University of Technology in Gothenburg, Sweden under the guidance of Professor Per Stenström. My research focuses on GPU architectures for approximate computing systems.

Diana Marculescu is Department Chair, Cockrell Family Chair for Engineering Leadership #5, and Professor, Motorola Regents Chair in Electrical and Computer Engineering #2, at the University of Texas at Austin.

Prior to joining UT Austin in December 2019, she was the David Edward Schramm Professor of Electrical and Computer Engineering, the Founding Director of the College of Engineering Center for Faculty Success (2015-2019) and has served as Associate Department Head for Academic Affairs in Electrical and Computer Engineering (2014-2018), all at Carnegie Mellon University.

She received the Dipl.Ing. degree in computer science from the Polytechnic University of Bucharest, Bucharest, Romania (1991), and the Ph.D. degree in computer engineering from the University of Southern California, Los Angeles, CA (1998). Her research interests include energy- and reliability-aware computing, hardware aware machine learning, and computing for sustainability and natural science applications.

Diana was a recipient of the National Science Foundation Faculty Career Award (2000-2004), the ACM SIGDA Technical Leadership Award (2003), the Carnegie Institute of Technology George Tallman Ladd Research Award (2004), and several best paper awards. She was an IEEE Circuits and Systems Society Distinguished Lecturer (2004-2005) and the Chair of the Association for Computing Machinery (ACM) Special Interest Group on Design Automation (2005-2009). Diana chaired several conferences and symposia in her area and is currently an Associate Editor for IEEE Transactions on Computers. She was selected as an ELATE Fellow (2013-2014), and is the recipient of an Australian Research Council Future Fellowship (2013-2017), the Marie R. Pistilli Women in EDA Achievement Award (2014), and the Barbara Lazarus Award from Carnegie Mellon University (2018). Diana is a Fellow of ACM and IEEE.

I recently finished my Ph.D.

My research interest is in computer architecture.

I am interested in parallel and heterogeneous architectures and application-specific accelerators, and how we can design and program them to continue improving application performance and efficiency in the face of limits to frequency and power scaling.

Currently serving as SiFive's VP of Hardware Engineering. Passionate about getting more women into the open source community. R & D interests include Chip Generators, Cryptographic Hardware, shared memory protocols, accelerating custom ASIC Design. Earned her Ph.D. in Electrical Engineering from Stanford University (w/ Prof. Mark Horowitz) and her undergraduate degree in Engineering from Brown University.

I'm a PhD student researching microarchitectural security and side-channel attacks in the CoreSec group at the IAIK, Graz University of Technology. Developing microarchitectural attacks and countermeasures has exposed me to many subfields of computer architecture. I'm particularly interested in ISA design and instruction decoding, the 'conflict' between energy efficiency and security, and whether we can rearchitect the CPU and the memory subsystem to reduce this conflict.

Natalie Enright Jerger is the Canada Research Chair in Computer Architecture and a Professor of Electrical and Computer Engineering at the University of Toronto. She is currently serving as the Director of the Division of Engineering Scinece at the University of Toronto. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008, respectively. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal recipient and the 2015 Borg Early Career Award winner. She served as the program co-chair of the 7th Network-on-Chip Symposium, as the program chair of the 20th International Symposium on High Performance Computer Architecture and as program co-chair for the International Conference on Architectural Support for Programming Languages and Operating Systems in 2023. She is currently serving as the ACM SIGARCH Chair. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. She is also passionate about increasing the representation of women in computing, particular in computer architecture. She is the former chair of the organizing committee for the Women in Computer Architecture group (WICARCH). In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. Her research has been supported by NSERC, Intel, CFI, AMD and Qualcomm.

My research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design for embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. In 2017, I have been elevated to the grade of IEEE Fellow “for contributions to energy-efficient computer architectures”. Recently I was European Project Coordinator of the H2020-FET-HPC project ANTAREX-671623 (2015-2018) on "Autotuning and adaptivity approach for energy efficient exascale HPC systems”. I was Project Coordinator of two other European projects: FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). I am an active member of the scientific community and I regularly serve in several international program committees. I annually teach basic and advanced courses on computer architectures and operating systems.

Thesis Title: LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Increasing processing demand has led to the development of chip multiprocessors which can have multiple to many cores connected with each other and with the on-chip caches. These connections are established by an on-chip packet-switched Network-on-Chip (NoC). Scaling of technology nodes increases the power dissipated by the chips leading to thermal restrictions. To control the chip thermal design power, certain components (like cores and caches) may be turned off. However, in this scenario of dark silicon, the interconnect is expected to be available.

The thesis aims to save power consumed by this always ON interconnect by replacing the power-hungry SRAM buffers in the routers with low leakage Non-Volatile Memory (NVM) based buffers. However, the major challenges with the employment of the NVMs are slower writes and weak write endurance.

The thesis proposes:
1. Methods to evenly distribute the writes across these NVM buffers in order to increase their lifetime. This is done by static and dynamic allocation of buffers to the virtual channels and their selection during packet transmission.

2. Power can also be saved by using frequency scaling of the routers and/or turning off certain buffers when the usage is less. The investigation is done for all such approaches and power savings are demonstrated.

3. Endurance can be improved and energy can be saved if we can reduce the number of writes performed on the buffers. This is achieved by proposing two compression techniques leading to reduced network traffic and improved lifetime.

All the above methods help in improving the lifetime of the NVM based NoC interconnects in the context of dark silicon.

Dr. Ghazal Tashakor is a scientific staff member affiliated with multiple institutes and universities in Germany and Spain. She obtained her Ph.D. in High-Performance Computing (HPC) and advanced simulation from the Autonomous University of Barcelona in 2019. Her ongoing research endeavors primarily focus on conducting large-scale computer simulations. Additionally, she serves as a core developer in distributed and parallel architecture patterns, ranging from grid computing to data visualization/monitoring, with a specific emphasis on Big Data and advanced hierarchical models. She collaborates with various research centers in Germany, including Fraunhofer and Jülich Supercomputing Centre (JSC)

Amila received her Bachelor's and Master's Degrees from the University of Sarajevo in Electrical Engineering within Computer Science and Informatics Department in 2006, 2009, respectively. In academic year 2007/2008 she received Fulbright Visiting Student Award and joined Embedded Systems and Architectures Lab at University California, Riverside as Junior Researcher. In 2010, she spent 1 month at Faculty of Electrical Engineering, University of Ljubljana as a visiting academic. Then, she received MEXT scholarship in 2010 and spend 3 and half years in beautiful Tokyo, where she completed her Ph.D. at Keio University in 2013.

Her primary area of interest is Computer Architecture, including Reconfigurable Architectures, High Performance Computing and Heterogeneous Computing. Her past research mainly focused on finding new ways to accelerate compute-intensive parts of an algorithm by means of offloading it to an FPGA. The challenge is to take advantage of knowledge about an architecture and adapt the algorithm to the architecture rather than the other way around. Her PhD research focused on developing architectures and methodologies that help to reduce the execution time of Cyclic Redundancy Check algorithms, particularly those implemented using FPGAs, and iSCSI protocol implementation.

In recent years, she has expanded her research to include Digital Signal Processing, Computer Vision, Image Segmentation, Machine Learning to name a few.

Rasha is a postdoctoral researcher at University of South Carolina. Beside, her research work, Rasha is the main instructor of embedded systems and computer architecture courses at Department of Computer Science and Engineering. Her primary research area is reconfigurable computing, embedded systems and application-specific architecture, specifically FPGA.

I am a PhD student at the University of California, San Diego, majoring in Computer Science and Engineering. My research interests lie in the intersection of Computer Architecture and Computational Genomics. I am a part of Turakhia Lab under the supervision of Professor Yatish Turakhia, where I work on solving computational challenges and developing efficient hardware for genomic data analysis. I completed my undergraduate in Electronics and Telecommunication Engineering from IIEST Shibpur, West Bengal, India.

As a computer science researcher specializing in computational genomics, I am dedicated to advancing the field through the development of optimized hardware+software accelerated tools. My research focuses on devising fully automated and scalable methods to accelerate error-prone phylogenetic estimation techniques. By doing so, I aim to contribute significantly to evolutionary biology studies and help unravel the complexities of the tree of life. In parallel, I am engaged in a fascinating project leveraging an HLS-based framework to accelerate dynamic programming-based algorithms, mainly focusing on sequence alignment algorithms. This project aims to help bioinformaticians customize their algorithms and port on FPGA with less effort, bringing significant advancements in computational genomics research.

Harini Muthukrishnan is a final year Ph.D. Candidate at the University of Michigan where she is advised by Prof. Tom Wenisch. Her research focuses on improving strong scaling in multi-GPU systems by optimizing fine-grained transfers and is in collaboration with Systems Architecture Research Group at NVIDIA Research.

Hi, my name is Peiqi Wang, a fourth-year Ph.D. candidate in computer science and technology from Tsinghua University, Beijing. I also have a one-year visiting experience in UCSB. My current research interests include accelerator architecture, computing with emerging devices, and deep learning optimization.

I am a 3rd year PhD student in the Department of Computer Science and Engineering at SUNY Buffalo. I work with Dr. Ramalingam Sridhar. My research interests include hardware security, memory systems and in-memory computing. I have completed my Masters in Electrical Engineering from SUNY Buffalo and Bachelors in Electronics and Communication Engineering from Karunya Institute of Technology and Sciences.

Sarita V. Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign. Her primary research interest is at the hardware-software interface with work spanning computer architecture, programming languages, operating systems, and applications. Her current research is on scalable system specialization and approximate computing.

She co-developed the memory consistency models for the C++ and Java programming languages, which are based on her early work on data-race-free (DRF) models. More recently, her work questioned the conventional wisdom for memory models for heterogeneous systems and showed that DRF is a superior model even for such systems. She is also known for her contributions to cache coherence (she co-developed the simple and efficient DeNovo coherence protocol); hardware reliability (she co-developed software-driven approaches for hardware reliability in the SWAT project and the concept of lifetime reliability aware architectures and dynamic reliability management in the RAMP project); power management (she led the design of GRACE, one of the first systems to implement cross-layer energy management); exploiting instruction-level parallelism (ILP) for memory system performance (she co-authored some of the first papers on exploiting ILP for memory level parallelism); and evaluation techniques for shared-memory multiprocessors with ILP processors (she led the development of the RSIM architecture simulator).

Professor Adve was named a Woman of Vision in innovation by the Anita Borg Institute for Women in Technology in 2012, an IEEE fellow in 2012, an ACM fellow in 2010, and received the ACM SIGARCH Maurice Wilkes award in 2008. For three of the last five years (2014-18), Illinois CS has selected her students' PhD theses as one of the department's two nominations for the ACM doctoral dissertation award. She currently serves as the chair of ACM SIGARCH, on the DARPA/ISAT study group, and on the board of directors of the Computing Research Association (CRA).

She received the Ph.D. and M.S. degrees in Computer Science from the University of Wisconsin - Madison in 1993 and 1989 respectively, and the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology - Bombay in 1987.

I'm a PhD student at Chalmers University of Technology in Gothenburg, Sweden. My current research focuses on scalable cache partitioning.

Mitali is a PhD student at Advanced Multicore Systems (AMS) lab, IIIT Delhi. She holds a gold medal in both Bachelor’s and Master's degrees. Her research interests include heterogeneous systems architectures and hardware security. She also works on designing efficient communication platforms for heterogeneous multi-core systems. She is currently focusing on design space optimization and security analysis of accelerator-rich heterogeneous system-on-chips (ArSoCs). Her recent works on energy-optimization of ArSoCs and SoC security were published in premier journals like TODAES'20 and TETC'21. She has published 1 book chapter and contributed to research works published in conferences including ASAP'18, ISCAS'18, ISVLSI'18, IGSC'18, ISCAS'20. She has experience of almost a year in academia as a lecturer and a research associate.

Sandhya Dwarkadas is the Walter N. Munster Professor and Chair of Computer Science at the University of Virginia. Previously, she was the Albert Arendt Hopeman Professor of Engineering at the University of Rochester, where she was professor of computer science with a secondary appointment in electrical and computer engineering, and also served as department chair for 6 years. She received the 2020 Edmund A. Hajim Outstanding Faculty Award from the University of Rochester. She received her Bachelor’s degree from the Indian Institute of Technology, Madras, India, and her M.S. and Ph.D. from Rice University. She is a fellow of the ACM and IEEE. She was co-chair of the CRA-WP board and steering committee from 2019-2022 and has been on the CRA-WP board since 2010.
Her areas of research interest include parallel and distributed computing, computer architecture, and the interaction and interface between the compiler, runtime/operating system, and underlying architecture. She has made fundamental contributions to the design and implementation of shared memory both in hardware and in software, and to hardware and software energy- and resource-aware configurability.

Aninda Manocha received her Ph.D student in Computer Science at Princeton University. She was advised by Professor Margaret Martonosi in the broad area of Computer Architecture. More specifically, she worked on the design of reconfigurable hardware to accelerate a variety of software applications with a focus on the application and compiler interface. She also worked on memory hierarchy designs and operating system techniques tailored to irregular, memory-intensive graph applications. She received her B.S. in Electrical and Computer Engineering as well as Computer Science from Duke University in 2018. She now works at Rivos.

Hai “Helen” Li is currently Clare Boothe Luce Associate Professor of Electrical and Computer Engineering Department at Duke University, USA. She received the B.S. and M.S. degrees from Tsinghua University, China, and the Ph.D. degree from the Department of Electrical and Computer Engineering, Purdue University, USA. Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li is a distinguished member of ACM, a distinguished speaker of ACM (2017-2020), and a distinguished lecture of IEEE CAS society (2018-2019).

I am an infrastructure engineer at Facebook. I graduated from Penn State with a PhD in 2019. I am interested in optimizing the physical infrastructure of a datacenter viz., power, compute, memory and storage. In my recent works I applied data analytics, system-level profiling and optimizations for efficient datacenter operations.

During PhD, I spent three summers as an intern at Microsoft Research which greatly shaped my research directions. My work on flash reliability titled, SSD failures in datacenters: What? When? Why? was awarded Best Student Paper at SYSTOR-2016. I have also received outstanding graduate research assistant award at Penn State in 2018.

I am a PhD candidate in the Computer Science Department at Georgia Institute of Technology advised by Professor Hadi Esmaeilzadeh. I received my Bachelors (2012) in Electrical Engineering from Indian Institute of Technology Ropar, India where I was honored with the President of India Gold medal for my outstanding academic performance. Subsequently, I completed my Masters (2014) from the University of Texas, at Austin in Electrical and Computer Engineering. I joined my PhD studies in Fall 2014 and since have been a part of Alternate Computing Technologies lab. My research interests include computer architecture, microarchitecture design, and developing alternative technologies for efficient computing. I am continuously working towards designing full stack solutions and template-based architectures for accelerating Machine Learning and Deep Learning algorithms on an FPGA. Besides my primary research-area of computer architecture, I have also worked at the intersection of machine learning, hardware design, programming languages and databases. In my free time, I like to spend time oil painting, cooking, and reading novels.

Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne.

My research focuses on bridging the gap between software and hardware with the purpose of building efficient circuits for Field Programmable Gate Arrays (FPGAs). I develop new high-level synthesis (HLS) techniques: the purpose is to generate hardware designs from high-level programming languages and to enable software developers to build efficient accelerators. I aim to change the HLS paradigm so that the produced circuits share key features with modern superscalar processors and are able to handle important classes of irregular and control-dominated applications.

I am grateful to have received the Google PhD Fellowship, the EPFL EDIC Fellowship, and the Google Anita Borg (Women Techmakers) Scholarship.

I am a PhD candidate in the Electrical and Computer Engineering department at Carnegie Mellon and a member of the ABSTRACT research group led by Professor Brandon Lucia. My research interests include computer architecture and hardware/software codesign for resource constrained, embedded devices. My current research focuses on programming and execution models for intermittently powered, energy harvesting devices.

Atefeh Mehrabi is a PhD student at ECE department of Duke University. She is co-advised by Prof. Sorin and Prof. Lee. Her research focuses in the area of computer architecture. More specifically, she is exploring and trying to tackle challenges of emerging reconfigurable accelerators. She got her B.Sc degree from University of Tehran in 2016 in Electrical Engineering and her M.Sc degree in Computer Engineering from Duke in 2018.

Amrita Mazumdar is a researcher at NVIDIA Research, working on topics at the intersection of graphics and video with computer systems and architecture. She received her PhD in Computer Science in May 2020 from the University of Washington, where she was advised by Luis Ceze and Mark Oskin. Her research interests are in computer systems and architecture for emerging visual computing workloads (e.g., VR and video analytics). Mazumdar’s work has resulted in performance improvements for custom hardware accelerators, storage systems, and data management systems. She received her MS (2017) from the University of Washington, and her BS (2014) from Columbia University. Prior to joining NVIDIA, Mazumdar founded a startup based on her PhD work, and has worked at Facebook, Oculus Research and IBM, as well as in collaboration with Google Research.

Darya Mikhailenko is pursuing a PhD in Electrical and Computer Engineering at the University of Rochester under the supervision of Prof. Engin Ipek. Her interests cover areas of energy-efficient computer architectures, machine learning for computer vision applications, memory management, accelerators, and architecture modeling for emerging technologies. Darya worked as a research assistant at Nanoelectronics Research Laboratory (Purdue University, U.S.A.) and Bioinspired Microelectronics Systems Laboratory (Nazarbayev University, Kazakhstan) on the implementation of brain-computer architecture to actualize deep neural networks. Her recent work was dedicated to techniques to minimize data movement energy by exploiting asymmetric on- and off-chip interconnects. Currently, she researches microarchitecture level optimizations for AR/VR applications.

Darya is looking for internships in the field of AR/VR related but not limited to computer architecture and machine learning algorithms.

PhD Student at University of Maryland, College Park, working on Emerging Technologies on Computer Architecture

EJ Kim is an Associate Professor in the Department of
Computer Science & Engineering, Texas A&M University, where she has been since 2003. She received the BS degree in computer science from the Korea
AdvancedInstitute of Science and Technology, Korea, in 1989, the MS degree in computer science from the Pohang University of Science and Technology, Korea, in
1994, and the PhD degree in computer science and engineering from the Pennsylvania
State University in 2003. Her research interests
include computer architecture, approximation computing, parallel/distributed systems, low-power design, secure computing, and performance evaluation.