Workshop on Energy-Secure System Architectures

Workshop on Energy-Secure System Architectures (ESSA)
in conjunction with HOST 2019
McLean, VA, USA
May 9-10, 2019

IMPORTANT DATES:
Submission Deadline: March 15, 2019 (extended)
Acceptance Decision: March 22, 2019
Final Submission: April 12, 2019
Presentation Slides: April 26, 2019 (unchanged)

The “power wall” has forced chip and system architects to design with smaller margins between nominal and worst-case operating points. Dynamic power, voltage noise and thermal management control loops have already become an integral part of chip and system design. New research papers in “wear out” and general reliability management have recently been published.

These new generation management protocols have, however, opened up other sources of concern: e.g. control loop stability and robustness of the management protocols. The potential security holes exposed by the integrated control loops and system safety issues triggered by potential violations of power or thermal limits are other areas of concern. Also, side channel attack scenarios enabled by modulated power profiles have been documented in prior research.

We seek to motivate the research community into adopting a holistic approach to mitigating the power wall and the concomitant reliability-security wall. We have coined the term “Energy-Secure System Architectures” to cover the range of research being pursued within industry and academia in order to ensure robust and secure functionality, while meeting the energy-related constraints of the “green computing” era. This segmented workshop offering, composed of lectures provided by experts in the areas of power/thermal management, reliability and security, provides a comprehensive view of the hardware and software aspects of Energy-Secure System Architectures

Topics of interest (but not limited to):
– Power, noise and thermal management solutions for modern multi-core platforms: with a focus on reliability and security challenges. 
– Verification and design for verification of system-level power, noise and thermal managers: predeployment safeguards against security breaches. 
– Reliability and security holes exposed by power/thermal management protocols: specific examples of attack scenarios. 
– Security-aware dynamic power management: software-hardware architectural concepts. 
– Use of machine learning/deep learning (ML/DL) principles in safeguarding against energy attacks in processors, server systems and data-centers. 
– Architectural implications of and system software support for energy-secure systems. 
– Security and reliability issues in emerging low power processor and memory technology. 
– Resilience and security challenges of ultra-low power cognitive IoT systems Energy-secure artificial intelligence (AI) systems. 
– Metrics for quantifying energy-security of computing systems. 

SUBMISSION GUIDELINES:
Extended Abstracts must be in English and up to 4 pages.
Accepted papers will be presented at the workshop and included in the workshop report.
Selected papers presented in the workshop will be invited to submit revised (updated) versions to a peer-reviewed special issue of IEEE Security and Privacy

ORGANIZERS:
Saibal Mukhopadhyay, Georgia Tech University, saibal@ece.gatech.edu
Pradip Bose, IBM T.J.Watson Research Center, pbose@us.ibm.com

Program Committee:
Saibal Mukhopadhyay, Georgia Tech University
Pradip Bose, IBM Research
Alper Buyuktosunoglu, IBM Research
Augusto Vega, IBM Research
Francisco J. Cazorla, Barcelona Supercomputing Center
Simha Sethumadhavan, Columbia University
Moinuddin Qureshi, Georgia Tech University
Edward Suh, Cornell University
Sanu Matthew, Intel Corporation