by SIGARCH Information Director on Mar 1, 2020 |

Call for Papers:

CARRV 2020

May 30, 2020 in Valencia, Spain
URL: https://carrv.github.io/

Final Submission Deadline
March 28, 2020

CARRV 2020: Workshop on Computer Architecture Research with RISC-V (with ISCA 2020)
May 30, 2020
Valencia, Spain

Submissions Due: March 28, 2020

The Fourth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

  • RISC-V cores and SoC architectures
  • RISC-V silicon characterizations and system designs
  • RISC-V simulation/emulation infrastructure
  • RISC-V ISA extensions
  • RISC-V-based hardware accelerators
  • Security architectures and techniques
  • Formal methods
  • Verification methodologies
  • Hardware/software interfaces
  • RISC-V ISA and implementation performance analysis
  • RISC-V compilers and dynamic translation tools

Important Dates
No abstract submission required
Full paper submission deadline: March 28, 2020, 23:59 PST
Author notification: April 11, 2020
Camera-ready version due: May 9, 2020