The 6th Workshop on Computer Architecture Research with RISC-V

The Sixth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and security evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

• RISC-V cores and SoC architectures
• RISC-V security
• RISC-V ISA extensions
• RISC-V-based hardware accelerators
• Security architectures and techniques
• Formal methods
• Verification methodologies
• Hardware/software interfaces
• RISC-V ISA and implementation performance analysis
• RISC-V compilers and dynamic translation tools