http://mpsoc.unife.it/~aistecs
in conjunction with HiPEAC 2017
Stockholm, Sweden
January 25, 2017
IMPORTANT DATES:
Submission deadline: October 30, 2016
Author notification: November 15, 2016
Camera-ready papers due: November 30, 2016
The AISTECS workshop promotes research and knowledge exchange on evolutionary as well as revolutionary interconnect technologies. This includes interconnect-related topics in the perspective of their adoption in future high performance systems and, in general, within future computing systems from servers/workstations down to embedded devices and the Internet of Things, which are tied to strict power budget and thermal envelopes because of the impending green computing era. To this end, the exploration of emerging interconnect technologies along with the design of disruptive/novel ideas at the microarchitectural network level are necessary, both leading to crucial challenges and interesting design tradeoffs for their widespread adoption in next-generation computing platforms. Furthermore, we expect that novel interconnect features have the potential to constitute disruptive new ideas able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives. Finally the workshop aims to increase the synergy to develop advanced interconnect solutions and technologies for emerging computing systems from a complete range of perspectives following a holistic approach: from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems. This encompasses novel network solutions from both academic and industrial researchers.
Workshop Topics:
– Networks on Chip (NoCs)
– Network architectures (topology, control-flow, routing, etc.)
– Silicon Photonics and Optical NoCs
– Interconnect solutions for heterogeneous GPU/FPGA-based multi/macro-chip systems
– Communication infrastructures for HPC systems, Supercomputers and Data Centers
– Emerging interconnect technologies (EIT): photonics, carbon nanotubes, through-silicon, RF, wireless NoC.
– Crucial challenges and design tradeoffs for EIT in future computer systems
– Low-level technological improvements and implications of EIT in future communication systems
– Thermal-/energy-and power-related NoC optimization and dark silicon
– Reconfigurable/programmable interconnect components
– Efficient interconnect for 2.5D and 3D packaging
– Asynchronous interconnect designs
– Clockless interconnects with focus on automation of their design methodology
– Network infrastructures for Internet-of-Things devices
– Architectures for QoS support and coherency
– Network solutions for performance isolation in many-core systems
– Impact of the interconnect on application performance
– Reliability, availability, fault tolerance for system communication
– Programming models for communication-centric systems
– Secure interconnection networks for intra-chip and inter-chip communication
– Efficient memory networks for large-scale workloads and Big Data applications
SUBMISSION GUIDELINES:
We invite contributions of previously unpublished results on the listed areas of future interconnect-centric systems, although not limited to them. We are interested in research, experimental, systems-related, survey, perspective and work-in-progress papers in all aspects of interconnects in general and emerging interconnect technologies/paradigms in particular at all levels of development.
Papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Papers must be formatted in accordance to the ACM two-column style. ACM Word or LaTeX style templates will be available on the website. Submissions must be limited to 4 pages. Papers deviating significantly from the paper size and formatting rules may be rejected without review.
Accepted papers will be published in the ACM Digital Library within the ACM International Conference Proceedings Series (ICPS). Authors will be sent the ACM form and instructions to finalize the camera-ready submission and to complete the publication procedure.
ORGANIZERS:
General Chairs:
– Sören Sonntag (Intel, Germany)
– José Manuel Garcia Carrasco (University of Murcia, Spain)
Program Chairs:
– José Luis Abellán Miguel (Catholic University of Murcia, Spain)
– Daniel Müller-Gritschneder (TU Munich, Germany)
Publication and Web Chair:
– Marco Balboni (University of Ferrara, Italy)
Steering Committee:
– Davide Bertozzi (University of Ferrara, Italy)
– Cyriel Minkenberg (Rockley Photonics, Switzerland)
Technical Program Committee:
– Sergi Abadal, Universitat Politècnica de Catalunya, Spain
– Federico Angiolini, iNoCS, Switzerland
– José Luis Ayala, Complutense University of Madrid, Spain
– Sandro Bartolini, University of Siena, Italy
– Giorgios Dimitrakopoulos, Democritus University of Thrace, Greece
– Holger Fröning, University of Heidelberg, Germany
– Francisco Gilabert, Intel, Germany
– Ajay Joshi, Boston University, USA
– David Kaeli, Northeastern University, USA
– John Kim, KAIST, South Korea
– Sébastien Le Beux, Lyon Institute of Nanotechnology (INL), France
– Sergei Mingaleev, VPIphotonics, Germany
– Chrysostomos Nicopoulos, University of Cyprus
– Sébastien Rumley, Columbia University, USA
– Jose Luis Sanchez Garcia, University of Castilla-La Mancha, Spain
– Laurent Schares, IBM, USA
– Johana Sepúlveda, TU Munich, Germany
– Federico Silla, Universitat Politécnica de Valencia, Spain
– Eitan Zahavi, Mellanox, Israel