MULTIPROG 2017

The Tenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016)
http://research.ac.upc.edu/multiprog/
in conjunction with HiPEAC
Stockholm, Sweden
January 24, 2017

IMPORTANT DATES:
Paper submission: October 21, 2016
Author notification: November 27, 2016

The ninth edition of the MULTIPROG workshop aims to bring together researchers interested in programming models, runtimes, and computer architecture. The workshop’s emphasis is on heterogeneous architectures and covers issues such as:
– How can future parallel programming models improve software productivity?
– How should compilers, runtimes and architectures support programming models and emerging applications?
– How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress, etc., and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop and online at the workshop’s web page.

Papers are sought on topics including, but not limited to:
1) Multi-core architectures
– Architectural support for compilers/programming models
– Processor (core) architecture and accelerators, in particular GPUs
– Memory system architecture
– Performance, power, temperature, and reliability issues
2) Heterogeneous computing
– Algorithms and data structures for heterogeneous systems
– Applications for heterogeneous computing and real-time graphics
3) Programming models for multi-core architectures
– Language extensions
– Run-time systems
– Compiler optimizations and techniques
4) Benchmarking of multi-/many-core architectures
– Tools for discovering and understanding parallelism
– Tools for understanding performance and debugging
– Case studies and performance evaluation

SUBMISSION GUIDELINES:
Submissions should not exceed 12 pages and should be formatted according to the LNCS format for CS Proceedings. This limit includes text, figures, tables and references. Please visit the workshop web site for detailed submission instructions.

ORGANIZERS:
Miquel Pericàs, Chalmers University of Technology
Vassilis Papaefstathiou, FORTH
Oscar Palomar, University of Manchester
Ferad Zyulkyarov, Barcelona Supercomputing Center

Program committee:
Abdelhalim Amer, Argonne National Lab
Ali Jannesari, UC Berkeley
Avi Mendelson, Technion
Chris Adeyeni-Jones, ARM
Christos Kotselidis, University of Manchester
Dong Ping Zhang, AMD
Håkan Grahn, Blekinge TH
Hans Vandierendonck, Queen’s University Belfast
Kenjiro Taura, University of Tokyo
Magnus Sjalander, NTNU
Oscar Plata, University of Malaga
Pedro Trancoso, University of Cyprus
Polyvios Pratikakis, FORTH-ICS
Roberto Gioiosa, PNNL
Sasa Tomic, IBM Research
Timothy G. Mattson, Intel
Trevor E. Carlson, Uppsala University
Yungang Bao, ICT-CAS