Workshop on Communication Optimizations in HPC

First International Workshop on Communication Optimizations in High Performance Computing (COMHPC)
https://software.intel.com/en-us/event/comhpc/2016/overview
co-located with SC16
in cooperation with ACM SIGHPC
Salt Lake City, Utah, USA
November 18, 2016

IMPORTANT DATES:
Submission deadline: September 8, 2016 AOE
Notification of Acceptance: September 28, 2016
Camera Ready copy: October 11, 2016
Workshop Date: November 18, 2016

As HPC applications scale to large supercomputing systems, their communication and synchronization need to be optimized in order to deliver high performance. In order to achieve this, capabilities of modern network interconnect and parallel runtime systems need to be advanced and the existing ones to be leveraged optimally. The workshop will bring together researchers and developers to present and discuss work on optimizing communication and synchronization in HPC applications. This includes state-of-the-art methodological and algorithmic advances in topology-aware or topology-oblivious blocking and non-blocking collective algorithms, offloading of communication to network interface cards, topology aware process mappings for minimizing communication overhead on different network topologies such as dragonfly, high-dimensional torus networks, fat trees, optimizations for persistent communication patterns, studies and solutions for inter-job network interference, overlapping of communication with computation, optimizing communication overhead in the presence of process imbalance, GPU-GPU and GPU-CPU communication. The workshop also aims at bringing researchers together to foster discussion, collaboration, and ideas for optimizing communication and synchronization that drive the design of future peta/exascale systems and of HPC applications. In addition, we expect that researchers and others looking for research directions in this area will get up-to-date with the state of the art so that they can drive their research in a manner that will impact the future of communication methods in high-performance computing.

Topics of interest for workshop submissions include (but are not limited to):
– Communication optimizations on Peta/Exascale systems, heterogeneous systems, and GPUs
– Scalable communication endpoints for many-core architectures
– Topology-aware collective algorithms and process mappings
– Communication offloading design and optimizations (such as offloaded triggered operations)
– Modeling and simulation of traffic patterns (including collectives) for generic/specific network topologies
– Blocking and non-blocking collective operations
– Neighborhood collective optimizations
– Optimizations for persistent communication patterns
– Inter-job network interference
– Computation-communication overlap in HPC applications
– Communication optimization in presence of process imbalance
– Static/runtime tuning of collective operations
– Network congestion studies and mitigation methods
– Machine learning to optimize communication
– Communication aspects of GPGPU
– Communication aspects of Graph Applications
– Communication aspects of Fault Tolerance

Keynote:
Prof. William Gropp, UIUC

SUBMISSION GUIDELINES:
Papers must follow the ACM format (see http://www.acm.org/sigs/publications/proceedings-templates). We invite two kinds of submissions to this workshop:
1. Full-length research papers (10-page limit)
2. Short papers (5-page limit), which can take the form of position papers, experience reports, work in progress, late breaking ideas, or surveys/comparisons

The page limit does not include references, for which there is no page limit. Papers should be submitted electronically via EasyChair: https://easychair.org/conferences/?conf=comhpc2016. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. Papers will be peer-reviewed by the Program Committee for novelty, scientific merit, technical strength, originality, quality of presentation and scope of the workshop. It is also expected that at least one author of an accepted paper must register for and attend the workshop. Accepted papers will be published in the workshop proceedings by SIGHPC and made available in the ACM Digital Library and IEEE Xplore. One outstanding paper will be selected for the Best Paper Award by the Program Committee.

ORGANIZERS:
Michael Chuvelev (Intel, Russia)
Daniel Faraj (SGI, USA)
Maria Garzaran (UIUC and Intel, USA )
Akhil Langer (Intel, USA)
Malek Musleh (Intel, USA)
Gengbin Zheng (Intel, USA)

Program Committee:
Ahmad Afsahi (Queen’s University, Canada)
George Almasi (IBM, USA)
Abhinav Bhatele (LLNL, USA)
Bill Gropp (University of Illinois Urbana-Champaign, USA)
Manish Gupta (Xerox Research Center, India)
Ram Huggahalli (Intel, USA)
Nikhil Jain (LLNL, USA)
David Lowenthal (University of Arizona, USA)
Vijay Pai (Google, USA)
D. K. Panda (Ohio State University, USA)
Sameh Sharkawi (IBM, USA)
Yogish Sabharwal (IBM, India)
Martin Schulz (LLNL, USA)
Bronis Supinski (LLNL, USA)
Sayantan Sur (Intel, USA)
Michela Taufer (University of Delaware, USA)
Keith Underwood (Intel, USA)
Abhinav Vishnu (PNNL, USA)
Alan Wagner (University of British Columbia, Canada)
Xin Yuan (Florida State University, USA)