Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Federico Silla
http://www.hucaa-workshop.org/hucaa2016

5th International Workshop on Heterogeneous and Unconventional
Cluster Architectures and Applications (HUCAA 2016)
in conjunction with ICPP 2016
Philadelphia, PA, USA
August 16, 2016
IMPORTANT DATES
Paper submission: March 21, 2016
Notification of acceptance: May 13, 2016
Camera-ready paper: June 3, 2016
Workshop: August 16, 2016
The workshop on Heterogeneous and Unconventional Cluster Architectures and
Applications gears to gather recent work on heterogeneous and unconventional
cluster architectures and applications, which might have an impact on future
mainstream cluster architectures. This includes any cluster architecture that
is not based on the usual commodity components and therefore makes use of
some special hard- or software elements, or that is used for special and
unconventional applications. In particular we call for GPUs and other
accelerators (Intel MIC/Xeon Phi, FPGA) used at cluster level. Even though
accelerators are already used pervasively, we still see many unconventional
and even disruptive uses of them.

Other examples of unconventional cluster architectures and applications
include virtualization, in-memory storage, hard- and software interactions,
run-times, databases, and device-to-device communication. We are in
particular encouraging work on disruptive approaches, which may show inferior
performance today but can already point out their performance potential. The
broad scope of the workshop facilitates submissions on unconventional uses of
hardware or software, gearing to gather ideas that are coming to life now and
not limiting them except for their context: clusters. Also, these proposals
may rather be reflective of a broader industry trend.

Topics of interest include any heterogeneous or unconventional cluster
architecture or application. Examples include, but are not limited to:
– Clustered GPUs, Xeon Phis or other accelerators
– Runtimes, resource management and scheduling for heterogeneous cluster
architectures
– Communication methods for distributed or clustered accelerators
– Energy-aware data movement techniques
– Energy efficiency at the cluster or node level
– New industry and technology trends and their potential impact
– High-performance, data-intensive, and power-aware computing
– Application-specific cluster and datacenter architectures
– Emerging programming paradigms for parallel heterogeneous computing
– Software cluster-level virtualization for consolidation purposes
– Hardware techniques for resource aggregation
– New uses of GPUs, FPGAs, and other specialized hardware

SUBMISSION GUIDELINES:
Submissions may not exceed 8 pages in PDF format including figures and
references, and must be formatted in the 2-column IEEE format. Submitted
papers must be original work that has not appeared in and is not under
consideration for another conference or journal. Work in progress is welcome,
but first results should be made available as a proof of concept. Submissions
only consisting of a proposal will be rejected. Please visit the workshop
website for additional details.

ORGANIZERS:
Workshop Co-Chairs:
– Federico Silla, Technical University of Valencia, Spain
– Holger Fröning, U. Heidelberg, Germany

Program Committee:
– Tarek Abdelrahman, U. Toronto, Canada
– José Luis Abellán, Catholic University of Murcia, Spain
– Olivier Aumage, INRIA, France
– José María Cecilia, Catholic University of Murcia, Spain
– Pierfrancesco Foglia, University of Pisa, Italy
– Basilio Fraguela, U. Coruna, Spain
– Efstratios Gallopoulos, University of Patras, Greece
– Marc Gonzalez, Universitat Politecnica de Catalunya, Spain
– Sascha Hunold, Technical University of Vienna, Austria
– Christos Kartsaklis, Oak Ridge National Lab, US
– Christoph Kessler, Linköping University, Sweden
– Tomàs Margalef, U. Autonoma Barcelona, Spain
– Gaspar Mora, Intel, US
– Thu D. Nguyen, U. Rutgers, US
– Dimitrios S. Nikolopoulos, Queen’s University, Belfast, UK
– Lena Oden, Argonne National Labs, US
– Alberto Ros, University of Murcia, Spain
– Dirk Pleiter, Research Center Jülich, Germany
– Alistar Rendell, Australian National University, Australia
– Etienne Riviere, University of Neuchatel, Switzerland
– Won Ro, Yonsei University, South Korea
– Antonio Robles, Technical University of Valencia, Spain
– Douglas Thain, U. Notre Dame, US
– Matthew Jacob Thazhuthaveetil, Indian Institute of Science, India
– Blesson Varghese, U. St Andrews, UK
– Shuangyang Yang, Louisiana State University, US

Steering Committee:
– José Duato, Technical University of Valencia, Spain
– Sudhakar Yalamanchili, Georgia Tech, US
– Ulrich Brüning, U. Heidelberg, Germany