IEEE MICRO Call for Papers: Special Issue on AI for Hardware and Hardware for AI

IEEE Micro seeks submissions for the upcoming special issue on “AI for Hardware and Hardware for AI”.

Submissions due: April 25, 2025

Publication: Nov/Dec 2025

For years, the computational landscape—stretching from data centers and supercomputers to simple home devices—has predominantly depended on general-purpose processors, which were sustainable while Moore’s law guaranteed that chip transistor counts would double approximately every two years. Today, however, as the pace of Moore’s law decelerates, we have witnessed an increasing shift toward hardware accelerators, designed to efficiently utilize hardware resources by concentrating solely on implementing the specific demands of target applications. Hardware accelerators, primarily engineered for an array of AI applications, from computer vision to recommendation systems and natural language processing, have been gaining traction, with substantial industrial investments and increasing scholarly interest. While the shift toward hardware accelerators has proven their capabilities, they face new challenges due to major AI growth. AI algorithms are not only scaling rapidly but also evolving at an accelerated rate. The scale and diversity of modern AI pose substantial challenges in the design of hardware accelerators. As a result, this IEEE Micro special issue seeks articles not only related to hardware accelerators for the next generation of AI but also to the exploration of how AI itself can facilitate the creation of cost-efficient, fast, and scalable hardware. This issue’s topics of interest include, but are not limited to:

• Scalable hardware accelerators for the next generation of large AI models
• Deploying new technologies (e.g., in-memory computing, photonics, analog computing) for AI efficiency
• Sparsity-aware optimization techniques for efficient AI
• Integration of AI techniques to expedite hardware/software co-design
• Rethinking the software/hardware stack for heterogeneous AI accelerator systems
• Interconnection networks and data movement optimizations for the future of AI
• Using AI methods to enhance the reliability of hardware accelerators, design validation, and architecture front-end and back-end
• Investigating security and privacy challenges in AI-assisted hardware accelerator design

Please find the submission guidelines at: https://www.computer.org/digital-library/magazines/mi/cfp-ai-hardware

Please contact the guest editor, Bahar Asgari, from the University of Maryland, College Park, at bahar@umd.edu, or the Editor-in-Chief, Hsien-Hsin Sean Lee, at lee.sean@gmail.com.