Workshop on Parallelism in Computer Arithmetic: From Circuits to GPU-Based Supercomputers
July 21, 2017
Workshop on Parallelism in Computer Arithmetic: From Circuits to GPU-Based Supercomputers
in conjunction with PACT
Portland, USA
September 9, 2017
IMPORTANT DATES:
Paper submission deadline: July 21, 2017
Notification of acceptance: August 11, 2017
Final PDF due: August 25, 2017
Some of the earliest parallel processing breakthroughs emerged from the quest for faster and higher-throughput arithmetic operations. Examples include carry-lookahead and several other fast addition algorithms, multi-operand addition, tree and array multipliers, recursive multiplication, convergence methods for division (and other functions of interest), arithmetic algorithms optimized for FPGA implementation, residue arithmetic, and modular operations on very wide operands for cryptographic applications. Additionally, the influence of arithmetic techniques on parallel computer performance can be seen in diverse areas such the bit-serial arithmetic units of early massively parallel SIMD computers, pipelining and pipeline-chaining in vector machines, design of floating-point standards to ensure the accuracy and portability of numerically-intensive programs, and prominence of GPUs in the design of today’s most-powerful supercomputers. This workshop aims to provide a representative sample of the many interactions and cross-fertilizations between computer-arithmetic and parallel-algorithms communities by presenting historical perspectives, case studies of state of art and practice, and directions for further collaboration.
ORGANIZER:
Behrooz Parhami, University of California – Santa Barbara