FPL 2015

Submitted by Kubilay Atasu
http://www.fpl2015.org

25th International Conference on Field Programmable Logic and
Applications (FPL2015)
The Royal Institution
London, UK
September 2-4, 2015
The International Conference on Field Programmable Logic and Applications (FPL)
is the first and the largest conference covering the rapidly growing area of
field-programmable logic. During the past 25 years, many of the advances in
reconfigurable system architectures, applications, processors, electronic
design automation (EDA) methods and tools have been first published in the
proceedings of the FPL conference series. The objective of FPL is to bring
together researchers and practitioners from both academia and industry from
around the world to share their insight into the frontiers of field-
programmable logic and its applications.

The 25th FPL Conference will take place at the Royal Institution, London, UK,
during September 2 – 4, 2015. Tutorials and associated workshops are offered on
August 31, September 1 and 4. A new angle of FPL 2015 is power efficient and
self-aware FPGA accelerators and heterogeneous computing platforms for High
Performance Computing, embedded systems and cyber physical systems. Highlights
of FPL 2015 will include keynotes from academia and industry.

FPL 2015 will offer the following FIVE CONFERENCE TRACKS:

1) ARCHITECTURES AND TECHNOLOGY
– Heterogeneous computing: multi/manycores, FPGAs, GPUs and DSPs
– Low power architectures
– Fault tolerant architectures
– Security and cryptography for FPGA Design
– 2.5D and 3D architectures
– Advanced on-chip interconnect technologies
– Analog and mixed-signal arrays
– Emerging technologies

2) APPLICATIONS AND BENCHMARKS
– Aerospace, automotive and industry automation
– Bioinformatics & medical systems
– Communications, software defined networking and Internet-of-Things
– Finance, HPC and database acceleration
– Big data analytics
– Embedded & cyber physical systems
– Signal processing and SDR
– Benchmarks for FPGA designs

3) DESIGN METHODS AND TOOLS
– System-level design tools
– High-level synthesis
– Hardware / software co-design
– Logic optimization and technology mapping
– Optimizations for power efficiency
– Packing, Placement and routing
– Rapid prototyping and emulation
– Testing, debugging and verification
– Open-source tools

4) SELF-AWARE AND ADAPTIVE SYSTEMS
– Self-awareness in FPGA-based systems
– Self-adaptive architectures and design techniques
– Virtualization of reconfigurable hardware
– Runtime resource management
– Partial reconfiguration

5) SURVEYS, TRENDS AND EDUCATION
– Surveys on reconfigurable logic architectures and design techniques
– Deployment of FPGAs in new application domains
– Roadmap of reconfigurable computing platforms
– Teaching courses and tutorials

IMPORTANT DATES:
Abstract Submission Deadline (mandatory): March 27, 2015
Full Paper Submission Deadline: April 3, 2015
Acceptance Notification: June 5, 2015
Camera-ready and Author Registration: June 26, 2015
Submission Instructions on: www.fpl2015.org

ORGANIZING COMMITTEE

General Chairs
Peter Cheung, Imperial College London, UK
Wayne Luk, Imperial College London, UK

Programme Chair
Cristina Silvano, Politecnico di Milano, IT

Track Chairs
Architectures and Technology
Jason H. Anderson, University of Toronto, CA
Applications and Benchmarks
Dirk Koch, University of Manchester, UK
Design Methods and Tools
Dirk Stroobandt, Ghent University, BE
Self-aware and Adaptive Systems
Marco Platzner, Paderborn University, DE
Surveys, Trends and Education
Walid Najjar, University of California at Riverside, US

Workshop & Tutorial Chairs
Guy Gogniat, Université de Bretagne-Sud, FR
Bob Stewart, University of Strathclyde, UK

Panel Chairs
Michael Huebner, Ruhr-Universitåt Bochum, DE
Simon Moore, University of Cambridge, UK

PhD Forum Chairs
Dimitrios Soudris, National TU of Athens, GR
Andy Tyrrell, University of York, UK

Demo Night & Project Presentation Chairs
Koen Bertels, TU Delft, NL
Jose Nunez-Yanez, University of Bristol, UK

Proceedings Chair
Walter Stechele, TU München, DE

Steering Committee
Jürgen Becker, KIT Karlsruhe, DE
Koen Bertels, TU Delft, NL
Eduardo Boemo, Univ. Autónoma de Madrid, ES
João M. P. Cardoso, Universidade do Porto, PT
Peter Y.K. Cheung, Imperial College London, UK
Martin Danek, Daiteq, CZ
Apostolos Dollas, TU of Crete, GR
Fabrizio Ferrandi, Politecnico di Milano, IT
Manfred Glesner, TU Darmstadt, DE
John Gray, Consultant, UK
Reiner Hartenstein, TU Kaiserslautern, DE
Andreas Herkersdorf, TU München, DE
Udo Kebschull, Goethe University Frankfurt, DE
Wayne Luk, Imperial College London, UK
Patrick Lysaght, Xilinx, Inc., US
Jari Nurmi, Tampere University of Technology, FI
Lionel Torres, University of Montpellier II, FR
Jim Tørresen, University of Oslo, NO