Call for Papers:

ICCD 2024

Abstract or Paper Registration Deadline
May 5, 2024
Final Submission Deadline
May 12, 2024

ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies. Authors are asked to submit technical papers in accordance with the submission guidelines (https://www.iccd-conf.com/Submission_guide.html)

in one of the following tracks:
Track 1: Computing Systems
System architectures; System support for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic, bio-inspired computing, machine learning, and artificial intelligence applications; Storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale systems, and serverless computing.

Track 2: Software Architectures, Compilers, and Tool Chains
Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systems; middleware for embedded systems, including resource awareness, reconfiguration, and energy/power management; compiler support for enhanced debugging, profiling, and traceability.

Track 3: Hardware Architectures
Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.

Track 4: Test, Verification, and Security
Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs;
Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test,
security and trust.

Track 5: Electronic Design Automation
System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clock tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.

Track 6: Logic and Circuit Design
Circuit design techniques for digital, memory, analog, and mixed-signal systems; Circuit design techniques for high performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing
technologies (MEMS, nano-spintronics, quantum, flexible electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits. A complete version of the paper should be submitted as a PDF file following the submission guidelines.

IMPORTANT DATES:
May 5 Abstract submission
May 12 Full paper submission
Aug 1 Notification of acceptance

Any questions about submission should be directed tothe Program Chairs, Benjamin Carrion Schaefer and Sara Vinco.
Please consult the ICCD 2024 website for additional information about the conference and submission details.