IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications

IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications

Submissions Due: December 15, 2019

IEEE Transactions on Computers seeks original manuscripts for a Special Issue on Domain-Specific Architectures for Emerging Applications scheduled to appear in May 2020.

Domain-specific architectures have gained prominence in the effort to overcome the stagnation in transistor feature-size scaling. The push towards greater performance and energy efficiency gains have necessitated in dedicated hardware focused on accelerating key application kernels. Such accelerators have proliferated, particularly in the machine learning and deep learning space, and are increasingly becoming essential components of mainstream commercial processors across a multitude of other domains as well. The rapid rate at which application and system software are evolving has also been reflected in processor design methodologies with most general-purpose computers being augmented with custom accelerators, both on and off-chip, making hardware-software co-development an essential component of the design and manufacturing flow. This IEEE Transactions on Computers Special Issue on Domain Specific Architectures for Emerging Applications seeks to expand our understanding of novel accelerator designs across emerging application domains, from circuit and microarchitecture aspects, to solutions at the compiler and system-software level.

Topics of interest to this special issue include, but not limited to:

• Novel accelerator designs catering to biomedical, healthcare, geospatial, industrial and manufacturing sectors, big data analytics, autonomous driving systems and other emerging domains
• Prototype demonstrations of field deployment-ready accelerators.
• Novel cloud-backed edge accelerator designs and architecture/system-software support thereof
• Special optimizations targeted towards maximizing energy efficiency and reliability of the accelerator
• Design of novel memory architectures for accelerators
• Leveraging emerging logic and memory technologies in accelerator designs
• Novel interconnect designs for heterogeneous accelerator-rich systems
• New agile design automation techniques for design and manufacturing of accelerator-rich systems
• Scalable distributed algorithms and architectures for homogeneous/heterogeneous accelerator swarms

Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. As an author, you are responsible for understanding and adhering to the Transactions submission guidelines. Those guidelines are available on the IEEE Computer Society web site, www.computer.org. Please thoroughly read these before submitting your manuscript. Please submit your paper to Manuscript Central at https://mc.manuscriptcentral.com/tc-cs

Please note the following important dates.

• Submission Deadline: December 15, 2019
• Reviews Completed: February 1, 2020
• Major Revisions Due: March 1, 2020
• Reviews of Revisions Completed: March 15, 2020
• Notification of Final Acceptance: March 15, 2020
• Publication Materials for Final Manuscripts Due: April 1, 2020
• Publication date: May 2020

Please address all other correspondence regarding this special session to Guest Editors Karthik Swaminathan (kvswamin@us.ibm.com) and Lisa Wu Wills (lisa@cs.duke.edu)