ParaFPGA 2015

Submitted by Erik D’Hollander
http://parafpga2015.elis.ugent.be

Parallel Computing with FPGAs (ParaFPGA 2015)
A Mini-Symposium held in conjunction with ParCo 2015
Edinburgh, UK

Conference date: 1-4 September 2015
Submission deadline : 1 June 2015
ParaFPGA2015 is a Mini-Symposium organized in conjunction with the
Biennial Parallel Computing conference ParCo2015, to be held in
Edinburgh, Scotland, UK on 1-4 September 2015.

SCOPE:

ParaFPGA focuses on parallel techniques for using FPGAs as
accelerator in high performance computing areas such as
supercomputing, embedded systems and big data computing.

Field Programmable Gate Arrays emerge as powerful building blocks for
High Performance Systems. The freedom to build tailored
architectures with extremely low power is one of the key milestones
on the path to exascale computing. Recently the major industrial
players invested heavily in high-level synthesis tools and
established well known programming paradigms to facilitate the march
towards programmable hardware. In addition, the famous memory wall
has been alleviated by incorporating processing cores inside the FPGA
fabric.

Of special interest are design methods, heterogeneous architectures
and algorithms optimized for execution on FPGAs. Design methods
include optimizing the resource utilization, development time and
high-level synthesis tools. Heterogeneous architectures encompass
multi-FPGAs, FPGAs with CPU cores and systems combining FPGAs, GPUs
and CPUs. Algorithms ready-made for FPGAs range from streaming
applications to fast dynamic reconfiguration and feature a
substantial performance increase.

Researchers and practitioners are invited to submit novel
contributions in the areas of high-level synthesis, dynamic
reconfiguration and high performance applications. Papers are
invited on a wide variety of topics related but not limited to:

– optimizing throughput of streaming applications
– non-uniform memory partitioning and data reuse
– heterogeneous on-chip processor and programmable logic codesign
– scalability of multi-core with multi-FPGA architectures
– OpenCL for FPGA applications
– evaluating performance metrics for high-level synthesis
– high-level synthesis techniques and case studies
– high-level partial and dynamic reconfiguration
– performance-driven resource and area optimization

SUBMISSION GUIDELINES:
Authors are invited to submit a full paper of maximum 10 pages or an
extended abstract of minimal 4 pages. The approved contributions
will be presented at the conference and the accepted full papers are
published in the ParCo 2015 proceedings. Details regarding the
format, presentation and paper submission are given on the author
guidelines page.

IMPORTANT DATES:
Submission deadline : 1 June 2015
Notification of acceptance : 15 July 2015
Final papers due : 15 August 2015

ORGANIZERS:
Steering committee:
– Gerhard Joubert, Conference Committee Chair
– Frans Peters, Finance Chair

Mini-Symposium committee:
– Dirk Stroobandt, Ghent University, Symposium chair
– Erik D’Hollander, Ghent University, Program committee chair
– Abdellah Touhafi, Brussels University, Program committee co-chair

Program committee:
– Abbes Amira, University of the West of Scotland, UK
– Georgi Gaydadjiev, Chalmers University of Technology
– Mike Hutton, Altera, USA
– Tsutomu Maruyama, University of Tsukuba, Japan
– Dionisios Pnevmatikos, Technical University of Crete, Greece
– Viktor Prasanna, University of Southern California, USA
– Mazen A. R. Saghir, Texas A&M University, Qatar
– Donatella Sciuto, Politecnico di Milano, Italy
– Sascha Uhrig, Technical University of Dortmund, Germany
– Sotirios G. Ziavras, New Jersey Institute of Technology, USA

CONTACT:
e-Mail: parafpga@elis.ugent.be
Website: http://www.parafpga2015.elis.ugent.be