Workshop on Computer Architecture Research with RISC-V

Second Workshop on Computer Architecture Research with RISC-V (CARRV)
co-located with ISCA 2018
Los Angeles, CA, USA
June 2, 2018

IMPORTANT DATES:
Abstract submission deadline: March 10, 2018
Full paper submission deadline: March 17, 2018 23:59 PST
Author notification: April 8, 2017
Camera-ready version due: May 19, 2018

The Second Workshop on Computer Architecture Research with RISC-V (CARRV) brings together researchers in fields related to computer architecture, compilers, and systems for technical exchange on using RISC-V in computer architecture research. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

– RISC-V simulation/emulation infrastructures, including ports of existing infrastructures
– Easily modifiable RISC-V RTL cores to support research
– Whole-SoC simulators/emulators and/or models built around RISC-V
– Machine-readable formal models and verification methodologies
– Compiler toolchains and operating system ports to support systems research
– RISC-V-based research prototypes
– Security architecture research
– Memory model research
– Quantitative comparison of RISC-V with other ISAs