Workshop on Multicore and Rack-scale Systems

Submitted by Boris Grot
http://www.cs.utexas.edu/~mars2016/

Workshop on Multicore and Rack-scale Systems (MARS)
co-located with EuroSys 2016
London, UK
April 18, 2016
IMPORTANT DATES:
Submission deadline: February 5, 2016
Acceptance Notification: March 9, 2016
Workshop date: April 18, 2016
Present and future multi-core architectures pose a variety of challenges for
system developers: non-cache-coherent memory, heterogeneous processing cores
and the exploitation of novel architectural features, such as systems-on-chip
(SoCs), distributed switching fabrics, silicon photonics, and programmable
hardware. In the near future, we expect to see “rack-scale computers” with
1,000s of cores and terabytes of memory, connected with bandwidth and latency
comparable to today’s smaller-scale NUMA servers.

MaRS 2016 is a forum for researchers in the hardware, networking, storage,
operating systems, language runtime and virtual machine communities to present
their experiences with and discuss innovative designs and implementations for
these new architectures.

Topics of interest include, but are not limited to:
– novel multi-core and rack-scale operating system designs,
– System-on-chip (SoC) and Network-on-chip (NoC) designs,
– runtime systems and programming environments for future hardware,
– low-latency and optical networking,
– OS or runtime support for heterogeneous processing cores,
– non-cache-coherent shared memory,
– scheduling on many-core and rack-scale architectures,
– programmable hardware,
– energy efficiency, fault tolerance and resource management on
future multi-core and rack-scale architectures,
– rack-scale storage,
– performance evaluation of emerging hardware,
– architectural support for systems-level software,
– case studies of system-level software design for current or future
multi-core and rack-scale hardware, and
– applications for and experiences with multi-core and rack-scale
systems.

PAPER SUBMISSION:
Authors are invited to submit original and unpublished work that exposes a
new problem, advocates a specific solution, or reports on actual experience.
Papers should be submitted using the standard two-column ACM SIG proceedings
or SIG alternate template, and are limited to 5 pages (including everything
except references). Additional pages can be used for references if required.
Papers that violate the submission guidelines may be rejected without
consideration of their merit.

Final papers will be made available to participants electronically at the
meeting, but to facilitate resubmission to more formal venues, no archival
proceedings will be published, and papers will not be sent to the ACM Digital
Library. Authors will be given the option of having their final paper
accessible from the workshop website. Authors of accepted papers will be
invited to give a talk at the workshop.

TALK SUBMISSION:
If you are interested in giving a talk at MaRS 2016, please submit a one-page
abstract instead of a full paper. Authors of accepted papers/talks will also
be invited to present a poster and/or demo in the EuroSys ’16 joint poster
session. Student speakers will be eligible to apply for EuroSys travel grants
to attend.

ORGANIZERS:
Boris Grot (University of Edinburgh)
Simon Peter (UT Austin)
Chris Rossbach (VMware and UT Austin)

Program Committee:
Mahesh Balakrishnan (Yale)
Antonio Barbalace (Virginia Tech)
Taesoo Kim (Georgia Tech)
Mark Oskin (University of Washington)
Mark Silberstein (Technion)
Cheng-Chun Tu (VMware)
John Wilkes (Google)
Bernard Wong (University of Waterloo)