Workshop on Network on Chip Architectures

12th International Workshop on Network on Chip Architectures (NoCArc)
in conjunction with MICRO 2019
Columbus, Ohio, USA
October 12-13, 2019

With the advancement in both computing architectures and process technology, many-core architectures can have thousands of cores into a single chip. This integration opens up a plethora of challenges, e.g., in terms of specialization and energy-focused implementations, and supports the spread of various applications and computational paradigms, ranging from multiprocessing to reconfigurable computing, from quantum computing to the emerging area of neuromorphic computing. Such wild increase in the number of processing elements (PE) per chip, together with the growing architectural and workload heterogeneity, calls for efficient, versatile, scalable and reliable communication infrastructures. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, the integration of a large number of PEs on a chip, or heterogeneous workloads. Novel techniques and architectures are needed to efficiently design and optimize the NoC and evaluate it at the network or system level.

The goal of NoCArc is to provide a forum for researchers to present and discuss innovative ideas and solutions related to the design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis, testing, and application of on-chip networks.

The workshop will focus on issues related to design, analysis, and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
– Topologies, routing, flow control
– Managing QoS
– Reliability issues
– Security issues
– Design methodologies and tools

NoC Analysis, Optimization, and Verification
– Power, energy and thermal issues
– Benchmarking with NoC-based systems
– Modeling, simulation, and synthesis
– Verification, debug and test of
– Metrics and benchmarks

NoC Applications
– Mapping of applications onto NoCs
– Real and industrial NoC case studies
– NoCs for FPGAs, ASICs, CMPs, and MPSoCs
– NoC designs for heterogeneous systems

NoC at System-level
– Design of memory subsystem
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing, or new models
– Large-scale systems (datacenters, supercomputers) with NoC-based Systems as building blocks

Emerging NoC Technologies
– Wireless, Optical, and RF
– NoCs for 3D and 2.5D packages
– Approximate computing for NoC and NoC-based systems

Machine Learning (ML) and NoC-based Systems
– Interconnects for ML systems/accelerators
– Memory access for the NoC-based ML systems
– NoC-based ML algorithm design

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

SUBMISSION GUIDELINES:
Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Submissions must be limited to 6 pages. Please, visit the workshop webpage (http://www.nocarc.org) for additional information about the submission process.

IMPORTANT DATES:
Abstract submission deadline: July 25, 2019
Paper submission deadline: August 1, 2019
Acceptance notification: September 1, 2019
Camera-ready version due: September 8, 2019
NoCArc workshop: October 12-13, 2019

ORGANIZERS:
General Chair:
Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Taiwan

TPC Co-Chairs:
Sergi Abadal, Universitat Politècnica de Catalunya, Spain
Salvatore Monteleone, University of Catania, Italy

Steering Committee:
Maurizio Palesi, Univ. of Catania, Italy
Davide Patti, Univ. of Catania, Italy
Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden
Masoud Daneshtalab, MDH and KTH, Sweden
Xiaohang Wang, South China University of Technology, China