Workshop on Pioneering Processor Paradigms

Second Workshop on Pioneering Processor Paradigms (WP3)
in conjunction with HPCA 2017
Vienna, Austria
February 25, 2018

IMPORTANT DATES:
Submission deadline: December 31, 2017
Notification of acceptance: January 14, 2018
Final paper submission: February 11, 2018
Workshop date: February 25, 2018

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. With this in mind, we present the second edition of the workshop on pioneering processor paradigms (P3). With the help of true pioneers as well as budding new researchers, P3 will take a retrospective look at how past technological hurdles were circumvented through major i nnovations. The goal is to learn from the past in devising new solution strategies for the future.

The P3 workshop will offer a number of invited talks from true pioneers as well as reviewed selections from the new generation of researchers and teachers who are eager to take a retrospective look into surveying past pioneering work that can teach us a lesson about solution strategies of the future.

The P3 workshop invites survey (or tutorial)-like submissions for review. The ideal paper would highlight a single pioneering paper (or set of papers) constituting a major processing, design, modeling or software paradigm shift in the past. In addition to explaining the context and basic concepts articulated in such work, the author(s) should draw relevant conclusions about how this pioneering work could or should influence computing paradigms of the future.

Note: Ph.D dissertation research topic proposals from (junior graduate students) that contain a survey of a key paper or two to build up the motivational justification of the proposal are welcome.

Topics of interest include (but are not limited to):
– Processing and cache taxonomy papers.
– RISC architectures and CISC-to-RISC dynamic translation support.
– Processor pipelining, super scalar processing and branch prediction innovations.
– Register renaming, out-of-order execution and precise interruption.
– Cycle-accurate processor performance modeling.
– Innovations in floating point arithmetic units and vector/SIMD acceleration.
– VLIW architectures.
– Multi-threading, multiscalar and speculative multi-threading.
– Homogeneous and heterogeneous multi-core processors; accelerator-enabled efficiency boost.
– Power, temperature, and reliability-aware computing – with associated modeling innovations.
– Compiler innovations in support of novel microarchitectural paradigms.
– Circuit design innovations in support of (micro)-architectural paradigm shifts.

ORGANIZERS:
John-David Wellman, IBM T. J. Watson Research Center
Ramon Bertran, IBM T. J. Watson Research Center
Robert Montoye, IBM T. J. Watson Research Center
Pradip Bose, IBM T. J. Watson Research Center