Workshop on Reconfigurable Acceleration in Datacenters

International Workshop on Reconfigurable Acceleration in Datacenters (ReconfigAccel)
in conjunction with ICS 2018
Beijing, China
June 12, 2018

IMPORTANT DATES:
Abstract submission: Apr 10, 2018, 11:59 PM (Pacific Time)
Author notification: May 1, 2018 (Pacific Time)
Workshop date: June 12, 2018 (Beijing Time)

With the slowdown of general-purpose processor scaling due to dark silicon limitations, customized hardware accelerators like FPGAs, CGRAs, and ASICs have gained increased attention in modern datacenters due to their lower power, high performance low latency, and energy efficiency. Evidenced by Microsoft’s FPGA deployment in its datacenters, FPGA-enabled public cloud announcements from Amazon, Alibaba, Baidu, Huawei and Tencent, as well as Google’s TPU cloud deployment, integrating customized hardware accelerators into datacenters is considered one of the most promising approaches to sustain future datacenter growth.

Deploying hardware accelerators in datacenters is still in its early stage and there are many research challenges ahead. For example, what kind of applications and workloads benefit from accelerators, how to program and manage such accelerators in the datacenter, and how to model and optimize these acceleration architectures? In this workshop, we plan to bring together academic and industry experts to share their experience, discuss challenges they face as well as potential focus areas for the community. Below is the planed workshop content.

Workshop topics:
We solicit extended abstracts (1 – 2 pages) from the community and selected ones will be invited to give a 20 mins talk with 10 min Q/A for each talk. Below is the proposed list of topics for the workshop. Note that primary focus for this workshop will be the emerging area of customized hardware accelerators such as FPGAs, CGRAs, and ASICs; there is already well chronicled research focus of GPUs in the datacenter. Workshop topics include, but are not limited to:
1. Large-scale application characterization, optimization, and evaluation, which leverage hardware accelerators, e.g., for machine learning, big data analytics, genomics, and video transcoding.
2. Programming models, compilers and debugging support to make it easier to program accelerators
3. Runtime and virtualization support to enable efficient deployment and scheduling of accelerators in datacenters
4. New acceleration architectures for datacenters, e.g., novel reconfigurable, programmable, low-power accelerator designs, near data acceleration architectures
5. Other research infrastructures (e.g., modeling/simulation/characterization) that enable the above studies

SUBMISSION GUIDELINES:
Interested authors are encouraged to submit extended abstracts (1 – 2 pages) by email to the organizing chair Dr. Zhenman Fang: zhenmanf@xilinx.com. Authors are encouraged to submit preliminary work for new projects and early results. Accepted abstracts will be invited to give a presentation at the workshop. The deadline for submission is Apr 10, 2018, 11:59 PM (Pacific Time).

ORGANIZERS:
Zhenman Fang, Xilinx, US (zhenmanf@xilinx.com)
Jim Hwang, Xilinx, US (jhwang@xilinx.com)
Leibo Liu, Tsinghua, China (liulb@tsinghua.edu.cn)
Wenwen Wang, University of Minnesota, US (wenwang@cs.umn.edu)