Archive of Calls for Participation
Information on registering and attending conferences, workshops and other events. Ordered by date posted on this website.
The ASPLOS 2025 / EuroSys 2025 Contest Track
The ASPLOS 2025 and EuroSys 2025 organizers are pleased to announce the ASPLOS 2025 / EuroSys 2025 Contest Track: a challenging, multi-month competition focused on advancing the state-of-the-art in multidisciplinary computer systems research. The high-Details…
Community Workshop on Practical Reproducibility in HPC
Registration is now open for the Community Workshop on Practical Reproducibility in HPC, taking place on November 18, 2024, in Atlanta, GA.
ICCD 2024
Call for Participation 2024 IEEE International Conference on Computer Design (ICCD) November 18 – 20, 2024 Milan, Italy https://www.iccd-conf.com/ ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems aDetails…
Memory-Centric Computing Systems Tutorial @ MICRO 2024
Memory-Centric Computing Systems Tutorial @ MICRO 2024 The tutorial will cover the latest advances in PIM technology, spanning both hardware and software, including novel PIM ideas, different tools and frameworks to conduct PIM research, and programming techniques and optimization strategies for PIM kernels. We’ll also have invited talks from leading industry and academic researchers in PIM systems. Stay tuned for the full program!
ESWEEK 2024
========================================================================= EMBEDDED SYSTEMS WEEK Call for Participation * CASES * CODES+ISSS * EMSOFT * MEMOCODE * Keynotes * * Workshops (LLM-PIM, MSC, RSP, TACPS, TCRS) * Tutorials * * Education Classes * Competitions * Panels * Raleigh, North Carolina, USA, September 29 – October 4, 2024 https://esweek.org/ ========================================================================= ————————————————————————- RECENT NEWS ————————————————————————- * The schedule overview and a preliminary program are available: https://esweek.org/schedule/ https://esweek.org/wp-content/uploads/2023/04/ESWEEK-2024-preliminary-program-1.pdf * The registration site is online (early registration deadline is August 30, 2024): https://esweek.org/registration/ ————————————————————————- About Embedded Systems Week (ESWEEK) ————————————————————————- Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (MEMOCODE), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development. Registered attendees can attend sessions in any of the ESWEEK conferences (CASES, CODES+ISSS, EMSOFT). Tutorials, symposium (MEMOCODE), and workshops can be registered individually or in addition with the ESWEEK registration. https://esweek.org/registration/ ESWEEK 2024 will take place as an in-person event from September 29th to October 4th, 2024 in Raleigh, North Carolina, USA. Prior to the main event, there are 6 education classes (virtual over zoom) to choose from on Friday, September 26th, 2024. Sunday starts with Tutorials and a welcome reception. The three main conferences, Keynotes, Special Sessions, Competition Sessions, Ph.D Forum and Recruitment Event take place on Monday to Wednesday, followed by Symposia and Workshops on Thursday/Friday. https://esweek.org/schedule/ https://esweek.org/wp-content/uploads/2023/04/ESWEEK-2024-preliminary-program-1.pdf
IISWC 2024
Join us for the 2024 edition of IISWC in Vancouver, Canada!
gem5 bootcamp 2024
The gem5 bootcamp offers an immersive workshop tailored for participants of all levels. Whether you’re a student or a professional, the inclusive program assumes no prior experience with gem5, aiming to provide a robust foundation for advanced research in computer architecture.
ISCA 2024 Call for Workshops & Tutorials
The dates for the workshops/tutorials are June 29-30, 2024. Submission deadline is Jan. 19, 2024.
ISCA 2024
In 2024, the 51st edition of ISCA will be held in Buenos Aires, Argentina, at the Hilton Buenos Aires during June 29 – July 3, 2024. This is a historic event as ISCA will be held in Latin America for the first time ever. Let’s make history together!
Memory-Centric Computing Systems @ ISCA 2024
Memory-Centric Computing Systems Tutorial In conjuction with ISCA 2024 at Buenos Aires, Argentina Saturday, June 29 The Memory-Centric Computing Systems tutorial will cover the latest advances in PIM technology, spanning both hardware and software, incDetails…
I2Q @ ISCA 2024
Tutorial: I too can Quantum (I2Q): Full Stack Fault Tolerant Quantum Computing Co-located with ISCA 2024 https://www.epiqc.cs.uchicago.edu/i2q-24 Quantum computing is a rapidly evolving field which in recent years has turned its focus to designing andDetails…
SEED 2024
International Symposium on Secure and Private Execution Environment Design (SEED) Orlando, Florida, USA May 16 – 17, 2024 Registration link http://seed-symposium.org The IEEE International Symposium on Secure and Private Execution Environment Design (SDetails…
ARCS 2024
========================================================================= C A L L F O R P A R T I C I P A T I O N — A R C S 2 0 2 4 37th GI/ITG International Conference on Architecture of Computing Systems May 14-16, 2024, Potsdam, Germany https://arcs-conference.org ========================================================================= The ARCS conferences series has over 36 years of tradition reporting leading edge research in computer architecture and operating systems. High performance computing represents an important tool for tackling climate change. In many other HPC application fields, the need for more high computing power has increased enormously in recent years, especially due to the high demand of AI-specific workloads. The operation of correspondingly powerful computing systems therefore represents an increasing problem in terms of energy requirements and the associated CO2 emissions. HPC is therefore not only part of the solution to tackling climate change, but also part of the overall problem. Heterogeneous computer architectures promise a significant increase in the energy efficiency of HPC systems. The selection of different accelerator architectures can contribute significantly to increasing efficiency, but there is currently a lack of appropriate concepts for their seamless and scalable integration, as well as the support through appropriate programming models. The focus of the ARCS’24 conference will be on novel accelerator architectures, which are suited for the integration into HPC systems. This includes fine and coarse grain reconfigurable architectures as well as new ideas for their integration to achieve higher energy efficiency as typical homogeneous architectures. In addition, the topics cover HPC-specific research at the level of computer architec- tures, runtime and operating systems, design tools and HPC programming models and algorithms. In addition to the main conference, ARCS will host special tracks on Organic Computing and Dependability and Fault Tolerance.
ISPASS 2024
ISPASS (IEEE Intl. Symposium on Performance Analysis of Systems and Software) is to be held on May 5-7 in Indianapolis, USA! Register for the conference, and make your hotel reservation no later than April 15th!
ASPLOS 2024
Conference Registration: https://whova.com/portal/registration/asplo_202403/ Hotel Registration: https://book.passkey.com/event/50611067/owner/10179/home
BioSys @ ASPLOS 2024
Inaugural BioSys workshop, Emerging Computer Systems Challenges and Applications in Biomedicine, In conjuction with ASPLOS 2024 at San Diego. This workshop presents a unique platform to discuss and explore exciting advancements in hardware acceleratorsDetails…
NVMW 2024
Nonvolatile Memories Workshop (NVMW 2024) will be held March 11-12 in San Diego, CA and the registration is now open!
FPGA 2024
The 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays March 3-5, 2024 Monterey, California, USA http://www.isfpga.org EARLY REGISTRATION ENDS FEBRUARY 8, 2024 https://www.isfpga.org/registration/ BOOK HOTEL NOW https://www.isfpgDetails…
ISFPGA 2024
The 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays March 3-5, 2024 Monterey, California, USA http://www.isfpga.or EARLY REGISTRATION ENDS FEBRUARY 8, 2024 https://www.isfpga.org/registration/ BOOK HOTEL NOW https://www.isfpga.Details…
HPCA 2024
30th IEEE International Symposium on High-Performance Computer Architecture (HPCA) H P C A 2 0 2 4 Edinburgh, UK March 2 – March 6, 2024 https://www.hpca-conf.org/2024/ The International Symposium on High-Performance Computer Architecture (HPCA) isDetails…
gem5 Architecture Simulator Tutorial @ HPCA 2024
6th gem5 Tutorial In conjunction with HPCA 2024 Register for the tutorial via HPCA’s registration process: https://hpca-conf.org/2024/. Early registration deadline: February 2nd. gem5 is the leading open-source computer architecture simulator, used inDetails…
PAW-ATM 2023: Parallel Applications Workshop, Alternatives To MPI+X
Alternatives to MPI+X are worth exploring as programmer productivity becomes a major component of the time to science. Alternatives include parallel programming languages (e.g. Chapel, Regent, Fortran 2018), general purpose libraries (e.g. Charm++, COMPSs, HPX, Legion, UPC++), and domain specific libraries (e.g. Arkouda, Dask, Spark). With many options to choose from, it is hard for programmers to know which alternative models are appropriate for their application and for programming model developers to understand the opportunities for improvement. Through discussion of specific applications, PAW-ATM brings together application experts and programming model developers to improve applications and models.
Real-World PIM Tutorial @ MICRO 2023
We would like to announce our upcoming online tutorial at MICRO 2023 on “Real-world Processing-in-Memory Systems for Modern Workloads”. Date: Sunday, October 29, 2023 (held during MICRO 2023, October 28 – November 1, 2023 in Toronto, Canada). TutorialDetails…
MAAD: ML-Assisted Architecture Design Tutorial @ MICRO 2023
Call for Participation We invite folks to attend our upcoming full-day MAAD tutorial at MICRO 2023 on “ML-Assisted Architecture Design: A Hands-On Experience.” Time & Date: Sunday, October 29, 2023 in Toronto, Canada from 8AM to 5PM. Tutorial OverDetails…
IISWC 2023
CALL FOR PARTICIPATION IEEE International Symposium on Workload Characterization (IISWC) — https://iiswc.org/iiswc2023/ Oct 1-3, 2023 — Ghent, Belgium IISWC is dedicated to the understanding and characterization of workloads that run on all types of coDetails…
ESWEEK 2023
========================================================================= EMBEDDED SYSTEMS WEEK Call for Participation * CASES * CODES+ISSS * EMSOFT * MEMOCODE * NOCS * Keynotes * * Workshops (CODAI, DOT-PIM, RSP) * Tutorials * Education Classes * * Ph.D. Forum and Recruitment Event * Competitions * Hamburg, Germany, September 17-22, 2023 https://esweek.org ========================================================================= ————————————————————————- About Embedded Systems Week (ESWEEK) ————————————————————————- Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (MEMOCODE, NOCS), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development. The 2023 edition of the Embedded Systems Week will take place on the campus of Hamburg University of Technology (TUHH), Germany. Prior to the main event, there are 13 education classes to choose from on Thursday and Friday. Sunday starts with Tutorials, the Diversity Event, and a Welcome Reception. The three main conferences, Keynotes, Competition Sessions, Ph.D Forum and Recruitment Event take place on Monday to Wednesday, followed by Symposia and Workshops on Thursday/Friday. ————————————————————————- NEWS / RECENT ————————————————————————- * Student Travel Grants (deadline: July 10th): https://esweek.org/student-travel-grants/ * Undergraduate Scholar Program (deadline: July 10th): https://esweek.org/undergraduate-scholar/ * Ph.D. Forum (deadline: July 14th) and ESWEEK Recruitment Events: https://esweek.org/esweek-ph-d-forum-and-recruitment-events/ * The ESWEEK registration is open. Advanced registration deadline is August 25. There are student travel supports. Check the ESWEEK webpage for more details. * The program is online: https://esweek.org/schedule/
NSF-CDER Instructor Training Workshop
NSF-CDER Instructor Training Workshop on Integrating Parallel & Distributed Computing (PDC) in Introductory Computer Engineering and Computer Science Classes https://www.ece.lsu.edu/vaidy/CDER-Workshop-LSU.htm July 31, 2023 to August 4, 2023 LouisiDetails…
Undergraduate Architecture Workshop (uArch) @ ISCA 2023
The Undergraduate Architecture Mentoring (uArch) Workshop is designed to introduce undergraduate and early Master’s students to research and career opportunities in the field of computer architecture in particular, and to graduate school lifestyle andDetails…
DSL-Based Hardware Generation (Calyx) Tutorial @ FCRC’23
This tutorial will show you how to build a DSL-to-hardware compiler using the Calyx compiler infrastructure.
AACBB-2023
5th Accelerator Architecture in Computational Biology and Bioinformatics workshop (AACBB-2023) June 18th, 2023 Orlando, Florida, USA In conjunction with the 50th International Symposium on Computer Architecture (ISCA-2023) Workshop website: https://aacDetails…
LCTES 2023
Call for Participation ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES 2023) Co-located with PLDI and FCRC 2023 Orlando, Florida June 18, 2023 https://pldi23.sigplan.org/home/LCTES-2023 LDetails…
Real-World PIM Tutorial @ ISCA 2023
Real-World PIM Tutorial at ISCA 2023 Date: Sunday, June 18, 2023 (held during ISCA 2023, June 17 – 21, Orlando, FL, USA) Website: https://events.safari.ethz.ch/isca-pim-tutorial/
ISCA 2023 (Orlando, June 17-21)
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and research results in computer architecture. This year is a particularly special year for ISCA as it celebrates its 50th anniversary! The 50th edition of IDetails…
PLARCH 2023
There is a growing overlap between PLDI and ISCA, and this workshop is convened to bring together people in that overlap.
Real-World PIM Tutorial at ASPLOS 2023
Real-World PIM Tutorial at ASPLOS 2023 Date: Sunday, March 26 2023 (held during ASPLOS 2023, March 25 – 29, Vancouver, Canada) Website: https://events.safari.ethz.ch/asplos-pim-tutorial/
FireSim and Chipyard User/Developer Workshop @ ASPLOS 2023
The FireSim and Chipyard user and developer community has experienced rapid growth, with significant cross-institution user and developer collaborations. This full-day workshop on March 26 at ASPLOS 2023 aims to bring together these communities to help drive the future direction of this ecosystem and spawn new collaborations. This workshop will feature talks from academic and industrial users of FireSim and Chipyard, across areas like computer architecture, systems, programming languages, and VLSI research/development. We hope that the presentations in this workshop will inspire lively discussion of FireSim/Chipyard governance, feature roadmaps, outreach activities, host platform specifications, and more.
ASPLOS 2023 Call for Participation
ASPLOS 2023 will be held primarily in person in Vancouver, BC. Please find out more information about the registration, remote attendance option, the conference venue, travel grants, and visa support in this link: https://asplos-conference.org/attend/
Non-Volatile Memories Workshop
The 14th Non-Volatile Memories Workshop will be held at UCSD on 3/13-14. Please register soon!
gem5 Tutorial at HPCA 2023
Date: February 25th 2023 (Saturday, Morning session) Location: HPCA, Montreal Webpage: https://www.gem5.org/events/hpca-2023 Registration: Please keep an eye on the HPCA website for registration information, https://hpca-conf.org/2023/ This event will give attendees a crash-course on using gem5 with no presumption of prior knowledge or usage of gem5. The tutorial is aimed at early-stage researchers but anyone interested is free to attend.
CGO 2023
ACM/IEEE International Symposium on Code Generation and Optimization (CGO 2023) Call for Participation Co-located with PPoPP, HPCA, and CC Montreal, Canada February 25 – March 1, 2023 https://www.cgo.org/ The International Symposium on Code GenerationDetails…
Workshop on Artificial Intelligence and Machine Learning for Scientific Applications at SC’22
[AI4S]: The 3rd Workshop on Artificial Intelligence and Machine Learning for Scientific Applications To be held in conjunction with SC22 Monday, 14 November 2022, 1:30pm – 5pm CST Kay Bailey Hutchison Convention Center, Dallas, TX, USA Website: https:/Details…
ESWEEK 2022
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (NOCS, MEMOCODE), and several workshops, tutorials, and education classes, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development. ESWEEK 2022 will be a week-long and truly hybrid event, with in-person and online events in Shanghai and Phoenix as well as online-only events. All sessions, except for offline social events, will be accessible through the ESWEEK Gather space. The program of ESWEEK 2022 will run from Oct 7-14, 2022, around the clock. A short teaser video (1 min) of each talk and a PDF file of each journal-track and work-in-progress (WiP) paper will be made available in the program two weeks before the conference. https://esweek.org/shanghai-program/ https://esweek.org/phoenix-program/ https://esweek.org/virtual-program/ Registered attendees can attend sessions in any of the online events, including three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (NOCS and MEMOCODE), tutorials, workshops, and education classes. Early registration deadline: Sept. 20, 2022, 12:00pm GMT https://esweek.org/registration/
IEEE/ACM MICRO-55
55th IEEE/ACM International Symposium on Microarchitecture (MICRO-55) October 1-5, 2022, Chicago, IL https://www.microarch.org/micro55/ The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debaDetails…
gem5 Boot Camp 2022
We are happy to announce the first gem5 Boot Camp, to be held at UC Davis from July 11th to July 15th 2022. The purpose of the gem5 Boot Camp is for junior computer architecture researchers, particularly PhD. students, to learn how to use gem5 in their projects. The Boot Camp, held over 5 days, will take attendees through setting up basic system simulations, creating bespoke components, learning to interpret gem5 stats, and up to running and modifying simulations comparable to real-world systems.
ICS 2022
Call For Participation ACM International Conference on Supercomputing (ICS 2022) June 27-30, 2022 Held virtually
ISA to ILA: Tutorial at ISCA 2022
Generalizing the ISA to the ILA A Software/Hardware Interface for Accelerator-rich Platforms Overview The Instruction-Set Architecture (ISA) has long served as the software/hardware interface for programmable processors. The ISA simultaneously serves aDetails…
ISCA 2022
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and research results in computer architecture. The 49th edition of ISCA has been pushed back a week from its original dates, and will now be held June 18-22Details…
AACBB 2022
We welcome you to take part in the 4th Accelerator Architecture in Computational Biology and Bioinformatics workshop (AACBB-2022) In conjunction with 49th IEEE International Symposium on Computer Architecture June 18th 2022 New York City, New York, USADetails…
uArch Workshop 2022
Applications for the Fourth Annual Undergrad Architecture Mentoring (uArch) Workshop are now open. The workshop is currently scheduled to be held in-person as part of the International Symposium on Computer Architecture (ISCA 2022), and is aimed at unDetails…
OCP ODSA HipChips Chiplet Workshop
The 1st International workshop on the High Performance Chiplet and Interconnect Architectures (code named “HipChips”), organized by the OCP Open Domain Specific Architecture (ODSA) Project Community, is a new workshop targeting research between academia and industry. This workshop helps researchers share the latest progress on chiplet-powered architectures for data-intensive applications and ML/HPC-motivated chiplet designs and helps promote the open chiplet standards to foster collaborations on further development of the chiplet ecosystem. The call for papers to present at the workshop is officially open. Submit your paper by email to: ISCAchiplets@opencompute.org by March 31, 2022.
ISPASS 2022 Tutorials
The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software. ISPASS 2022Details…
FCCM’22 Call for Participation (Early Registration by May 1)
Call for Participation: The 30th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) May 15–18, 2022 | New York City | Hybrid Event The IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)Details…
Call for Participation: HPCA 2022
Call for Participation: HPCA 2022 https://hpca-conf.org/2022/ Main Program: https://hpca-conf.org/2022/program/ Keynotes: https://hpca-conf.org/2022/keynotes/ Workshops/Tutorials: https://hpca-conf.org/2022/workshops-tutorials/ Register here: https://wDetails…
CGO 2022
IEEE/ACM International Symposium on Code Generation and Optimization (CGO) co-located with PPoPP, CC, and HPCA Virtual Conference April 2 – 6, 2022 https://cgo.org/ ** With the continued impact of the COVID-19, the joint steering committee of CGO/PPoPPDetails…
DATE 2022
+++Check out the Detailed Programme at https://www.date-conference.com/programme+++ +++Register here https://www.date-conference.com/registration+++ Dear community We would like to announce that the detailed programme of DATE 2022 is available online and cordially invite registrations to join us in celebrating another exciting edition of the conference – the top scientific event in Design, Automation and Test of microelectronics and embedded systems for the academic and industrial research communities worldwide!
Tutorial on Serverless and vHive at ASPLOS 2022
This tutorial provides an overview of serverless cloud computing and introduces the vHive ecosystem, a full-stack open-source framework for serverless experimentation and innovation. The tutorial seeks to educate the participants about serverless computing and benchmarking methodology, and teach the researchers from the computer architecture and computer systems community to use vHive for their research.
ISFPGA 2022
The 30th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) 2022 is a virtual conference to be held from February 27 – March 1, 2022. The virtual conference will feature a two-day main program and four interesting workshops/tutoDetails…
NAS 2021
The 2021 IEEE International Conference on Networking, Architecture and Storage will be held during 24-26 October 2021 in Riverside, CA, USA. Important Dates: Advance Registration deadline: September 30, 2021. Registration details can be found here: http://www.nas-conference.org/NAS-2021/registration.html
ICCD 2021
Call for Participation The 39th IEEE International Conference on Computer Design (ICCD) October 24 – 27, 2021 Virtual Conference http://www.iccd-conf.com We invite you to join us for the International Conference on Computer Design (ICCD), which will taDetails…
MICRO 2021
IEEE/ACM International Symposium on Microarchitecture (MICRO-54) 18-22 October 2021, Global Online Event broadcast from Athens https://www.microarch.org/micro54/ The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenDetails…
NOCS 2021
15th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2021) October 14-15, 2021, Virtual Conference https://nocs2021.github.io/index.html About NOCS The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to inteDetails…
ESWEEK 2021
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems, and it brings three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (NOCS), and several workshops and tutorials.
PACT 2021
Virtual PACT 2021 conference starts with a workshop on September 26 and continues with a tutorial on September 27 and the main conference during September 27th – 29th. We have an exciting program this year with one keynote talk (Saman Amarasinghe, MIT) and 25 papers. The details are on the PACT 2021 website (http://pactconf.org/) where you can register for the conference.
SEED 2021
The IEEE International Symposium on Secure and Private Execution Environment Design (SEED) September 20-21, 2021 – Virtual https://www.seed-symposium.org/ Registration Link: https://cvent.me/YPqWZb The IEEE International Symposium on Secure and PrivateDetails…
ISVLSI 2021
The IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2021) will be held virtually from July 7-9, 2021. ISVLSI 2021 features four keynote speakers, 8 oral paper sessions, 4 special sessions, 1 poster session, and 1 panel.
ASAP 2021
The 32nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2021) will be held on July 7-8, 2021. ASAP 2021 will go virtual this year, and features three keynote speakers, four oral paper sessions, two special sessions, two poster sessions, and one pane
uArch Workshop
Applications for funding to attend the Third Annual Undergrad Architecture Mentoring (uArch) Workshop and International Symposium on Computer Architecture (ISCA) are now open. The funding will cover the registration fee for attending the workshop and cDetails…
CF 2021
18th ACM International Conference on Computing Frontiers (CF’21) May 11-13, 2021 – Virtual Conference http://www.computingfrontiers.org/ Technical Co-Sponsor: ACM, SIGMICRO Financial Sponsors: ARM, Intel, SambaNova Systems, Tactical Computing Labs TheDetails…
FCCM 2021
The 29th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2021) May 9 – 12th, 2021 Early registration is due on April 26, 2021 Registration website: https://www.fccm.org/registration/ Main program: http://www.fccm.org/programs-/#maiDetails…
Data Science Day 2021 at Columbia University
Data Science Day provides a forum for innovators in academia, industry, and government to connect. The April 21, 2021 virtual event will feature two sessions of lightning talks from leading Columbia University faculty members; interactive demonstrations and posters; and a keynote address from Pat Bajari, a Chief Economist at Amazon and Vice President of Amazon’s Core AI team.
RSS2: Workshop on Robustness and Safe Software 2.0.
Unlike Software 1.0 (conventional programs) that is manually coded with hardened parameters and explicit logics, Software 2.0 programs, usually manifested as and enabled by Deep Neural Networks (DNN), have learnt parameters and implicit logics.
ASPLOS 2021
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021) April 12-23, 2021 Virtual ASPLOS 2021 registration is open! ASPLOS is the premier forum for interdisciplinary systems research, intersectingDetails…
ISPASS 2021
The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software.
tinyML Summit and Research Symposium
https://form.jotform.com/210112778977059?src=vjr
Compiler Construction (CC) 2021
The International Conference on Compiler Construction (CC) is interested in work on processing programs in the most general sense: analyzing, transforming or executing input that describes how a system operates, including traditional compiler construction as a special case.
CGO 2021
The International Symposium on Code Generation and Optimization (CGO) is a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.
HPCA 2021
The 27th International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field.
PPoPP 2021
PPoPP is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience.
3rd AccML Workshop at HiPEAC 2021
In this 3rd AccML workshop, we aim to bring together researchers working in Machine Learning and System Architecture to discuss requirements, opportunities, challenges and next steps in developing novel approaches for machine learning systems.
Machine Learning in Science & Engineering – MLSE 2020
Machine Learning in Science & Engineering (MLSE 2020) will feature the latest research in artificial intelligence and machine learning that are advancing science, engineering, and technology fields at large. Use code MLSE2020 for 30% off tickets.
IISWC 2020
Welcome to 2020 IEEE International Symposium on Workload Characterization (IISWC 2020)! IISWC 2020 will be held on October 27-29, 2020 in a virtual format. The registration website is open, you can Register Now! Early registration rates end 12 October, 2020.
ICCD 2020
We invite you to join us for the International Conference on Computer Design (ICCD), which will take place in virtual space on October 18-21, 2020. ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components.
NoCArc 2020 (Global Online Event, October 18, 2020)
NoCArc 2020 IEEE/ACM 13th International Workshop on Network on Chip Architectures. (http://www.nocarc.org/) To be held in conjunction with the 53rd Annual IEEE/ACM International Symposium on Microarchitecture® October 18, 2020, Global Online Event RegiDetails…
Persistent Programming In Real Life 2020
Persistent Programming In Real Life (PIRL) 2020 brings (virtually) together software development leaders interested in learning about programming methodologies for persistent memories and sharing their experiences with others. This is a meeting for developer project leads on the front lines of persistent programming, not sales, marketing, or non-technical management. This month-long virtual event will enable leaders to learn what their peers have done, and want to do, with persistent memory, what worked, what was hard, and what was surprising.
PACT 2020
The registration for the 29th International Conference on Parallel Architectures and Compilation Techniques (PACT) is now open. Registration includes the main conference, along with access to all recordings of talks, Q&A sessions, and keynotes through October 31 2020. Workshops and tutorials are free.
PACT 2020
We invite you to participate in the virtual PACT 2020 conference, which starts with a workshop and tutorial on October 2nd, and the main conference during October 5th – 7th. We have an exciting program this year with 3 keynote talks, 2 panels, 35 papers and 16 poster presentations.
NOCS 2020
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems.
MICRO-53
53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53) 17-21 October 2020, Global Online Event https://www.microarch.org/micro53/ The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing,Details…
CONCUR 2020
The 31st International Conference on Concurrency Theory (CONCUR) will be held online on 1-4 September 2020. The purpose of the CONCUR conferences is to bring together researchers, developers, and students in order to advance the theory of concurrency, and promote its applications. It is held as part of the QONFEST 2020, the umbrella conference comprising the joint international 2020 meetings alongside with several workshops and tutorials.
ISPASS 2020
The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. Due to the global pandemic, ISPASS 2020 will be held as a virtual conference August 24 through 26, 2020. The conference will include pre-recorded paper talks available online, as well as live portions during those mornings (EDT).
ROAD4NN: Workshop at DAC 2020
In the RAOD4NN workshop, we focus on the open research problems of automatic design for neural networks, where we discuss full stack open source infrastructure support to develop and deploy novel neural networks, including novel algorithms and applications, hardware architectures and emerging devices, hardware-software co-design, as well as programming, compiler, system, and tool support. We will bring together academic and industry experts to share their experience, discuss challenges they face as well as potential focus areas for the community.
ICS 2020 Call for participation
The ACM International Conference on Supercomputing (ICS) is the premier international forum for the presentation of research results in high-performance computing systems. The 34th conference (ICS-2020) was planned to be held in Barcelona, Spain and co-organized by the Universitat Politecnica de Catalunya (UPC-BarcelonaTECH) and the Barcelona Supercomputing Center (BSC-CNS). Because of the COVID-19 outbreak, the event will be held worldwide in a virtual format.
ISCA Undergrad Mentoring Workshop 2020
Applications for funding to attend the Second Annual Computer Architecture Undergraduate Mentoring Workshop are now open. The workshop will be held as part of ISCA 2020, and is aimed at undergraduate students with an interest in computer architecture. We expect the workshop will most benefit students who will receive their undergraduate degree in 2021 or 2022, and funding priority will go to students from Europe, the Middle East, and Africa. Women and underrepresented minorities are particularly encouraged to apply for funding.
HPBDC 2020
International Workshop on High-Performance Big Data, Deep Learning, and Cloud Computing (HPBDC), aims to bring HPC, Big Data processing, Deep Learning, and Cloud Computing into a convergent trajectory. The workshop provides a forum for scientists and engineers in academia and industry to present their latest research findings in major and emerging topics for ‘HPC + Big Data + Deep Learning over HPC Clusters and Clouds’. HPBDC 2020 will be held in conjunction with the 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2020).
CLOSER 2020
The 10th International Conference on Cloud Computing and Services Science, CLOSER 2020, focuses on the highly important area of Cloud Computing.
ISPASS 2020
The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. ISPASS 2020 will be held April 5 through 7, 2020 in Boston, MA.
ASPLOS 2020
ASPLOS 2020 Program is now online: https://asplos-conference.org/home/programs/ Early registration deadline is Feb 24: https://asplos-conference.org/attend/
DATE 2020
Call for participation: Design, Automation and Test in Europe Conference (DATE 2020)
DATE 2020
+++ DATE 2020 Deadline Early-Bird Registration: 5 February 2020, 23:59:59 CET +++ Dear colleagues, DATE 2020 is approaching fast and so is the deadline for the early-bird registration. Register online NOW in order to benefit from the early-bird registrDetails…
Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
This workshop focuses on the architecture and design of hardware and software accelerators for computational biology and bioinformatics problems.
HPCA 2020
HPCA Registration Website is up (Early Registration ends on Jan 31) – https://www.hpca-conf.org/2020/registration/ Reserve the hotel at – https://www.hpca-conf.org/2020/venue-hotel/ -HPCA Team See you all in San Diego!
Chisel Community Conference 2020
We’re happy to announce that we’ll be having a 3rd Chisel Community Conference (hosted by CHIPS Alliance) on January 29–30, 2020 at the Western Digital campus in Milpitas, CA.
Chisel Community Conference 2020
Update: Proposal/talk submission deadline extended until December 12th, 2019. Proposals will be accepted on a rolling basis to provide time for international travel considerations.
WACCPD 2019: Sixth Workshop on Accelerator Programming using Directives
We cordially invite you to attend the 6th Workshop on Accelerator Programming using Directives (WACCPD 2019) and look forward to seeing you there!
PAW-ATM: Parallel Applications Workshop, Alternatives To MPI+X
The PAW-ATM workshop is designed to explore the expression of applications in scalable parallel programming models that serve as an alternative to the status quo. It is designed to bring together applications experts and proponents of high-level programming models to present concrete and practical examples of using such alternative models and to illustrate the benefits of high-level approaches to scalable programming.
NOCS 2019
13th IEEE/ACM International Symposium on Networks-on-Chip Oct 17-18, 2019; co-located with ESWEEK 2019, New York, NY, USA https://www.engr.colostate.edu/nocs2019/ The conference program includes several keynotes, tutorials, special sessions and regular paper session with participants from industry and academia. We hope you are able to attend!
MICRO 2019
We cordially invite you to attend the 52nd edition of MICRO, to be held in Columbus, Ohio, October 12-16, 2019 at the Hilton/Greater Columbus Convention Center.
Persistent Programming In Real Life
PIRL brings together software development leaders interested in learning about programming methodologies for persistent memories (e.g. NVDIMMs, Optane DC) and sharing their experiences with others. This is a meeting for developer project leads on the front lines of persistent programming, not sales, marketing, or non-technical management.
ASAP 2019
ASAP 2019 – Call for Participation
SIGARCH Visioning Workshop: Agile and Open Hardware for Next-Generation Computing
A Golden Age: Moore’s Law, after transforming our world for more than 50 years, has finally started to slow down. John Hennessy and David Patterson welcomed this trend in their Turing Award lecture as this slowdown will bring about a new golden age of computer architecture. Since achieving continued performance improvements through transistor scaling provides less economic benefit, the computing industry must increasingly rely on vertically integrated solutions with domain-specific accelerators to continue improving computing performance. However, the high engineering cost, including tools, labor, and IPs, has prohibited the wide adoption of specialized architectures for all applications except a few designs that can amortize the high cost. Been There, Done That: Compared to the hardware industry, the software community has embraced agile software development and open-source software design for decades. In fact, open-source software has become a critical component of today’s major software infrastructure. As a result, a small team of software developers can leverage a rich ecosystem of reusable, open-source components and use high-level abstractions to realize their innovative ideas quickly. This has significantly reduced the engineering cost, shortened the design cycles, and enabled the proliferation of software startups. Time to Dive In: Agile and open hardware design is one of the most promising ways to lower the design cost and sustain future computing performance growth. Agile hardware design abstracts hardware implementation to a higher level and enables fast iterations of continuous hardware development. Open source hardware provides a pool of off-the-shelf components that enables further system-level integration. We believe the architecture and system community should take the leadership role of realizing agile and open hardware design. Goals: * Advocate for the system and architecture community to make agile and open-source design a centerpiece of the academic enterprise. * Share the successful experience from software community on initiating and managing open-source software projects. * Introduce ongoing efforts in systems, architecture, and EDA communities on agile and open hardware design. Tentative Schedule: 9:00 am – 9:05 am, Organizers 9:05 am – 9:40 am, David Patterson, UC Berkeley/Google 9:40 am – 10:15 am, Vivienne Sze , MIT 10:15 am – 10:50 am, Andrew Kahng, UCSD 10:50 am – 11:20 am, Coffee Break 11:20 am – 11:55 am, Richard Ho, Google 11:55 am – 12:30 pm, Yungang Bao, Chinese Academy of Sciences 12:30 pm – 2:00 pm, Lunch Break 2:00 pm – 2:30 pm, Mark Horowitz, Stanford, 2:30 pm – 3:00 pm, Jason Cong, UCLA 3:00 pm – 3:30 pm, Brucek Khailany, NVIDIA 3:30 pm – 4:00 pm, Coffee Break 4:00 pm – 4:30 pm, Bora Nikolic, UC Berkeley 4:30 pm – 5:00 pm, Adam Chilpala, MIT Organizers: Christopher Batten, Associate Professor, Cornell University Yunsup Lee, Chief Technology Officer, SiFive Yakun Sophia Shao, Research Scientist, NVIDIA
Tutorial on OpenPiton and Ariane: The RISC-V Hardware Research Platform
OpenPiton+Ariane is a permissively-licensed open-source framework designed to enable scalable architecture research prototypes. With the recent addition of SMP Linux running on FPGA, OpenPiton+Ariane is the first Linux-booting, open-source, RISC-V system that scales from single-core to manycore. Building on the maturity of the OpenPiton platform and the Ariane 64-bit RISC-V processor, OpenPiton+Ariane is the ideal RISC-V hardware research platform. On Sunday June 23rd at ISCA/FCRC 2019 we will be holding a half-day afternoon tutorial to get interested users acquainted with the platform. This is a hands-on session which will first introduce attendees to our validation infrastructure using open-source simulators. Attendees will also learn how to synthesise multiple cores to FPGA and get direct experience with booting multicore Linux on our provided FPGAs. We will also teach attendees how to configure and extend the OpenPiton architecture to enable architecture research. Register for the tutorial and enjoy an early registration discount until May 24th (https://iscaconf.org/isca2019/registration.html). More details on our tutorial are available at http://parallel.princeton.edu/openpiton/ISCA19_tutorial.html
Tutorial on Methods for Characterization and Analysis of Voltage Margins in Multicore Processors
Tutorial on Voltage Margins in Modern Multicore Microprocessors and Methods for their Characterization and Analysis. ACM/IEEE International Symposium on Computer Architecture, Sunday 23 June, 2019, Phoenix, AZ, USA. http://isca46.tutorial.di.uoa.gr/
Tutorial on Accelerating Big Data Processing and Associated Deep Learning on Modern Datacenters
Accelerating Big Data Processing and Associated Deep Learning on Modern Datacenters
Workshop on Computer Architecture Research Directions
CARD 2019 presents three mini-panels consisting of three experts in the field, two as panelists and the third as a moderator/panelist. The purpose of this workshop is to serve as a forum in which experts in each field can debate the state of the field and future directions.
ISCA 2019
The 46th International Symposium on Computer Architecture (ISCA) Phoenix, Arizona, USA June 22-26, 2019 ISCA-2019 will be co-located with FCRC-2019 (https://fcrc.acm.org/), with Geoffrey Hinton and Yann LeCun to deliver the Turing Lecture. The conferenDetails…
Tutorial on Demystifying Memory Models Across the Computing Stack
Do you find memory models inscrutable? Does your parallel program or processor mysteriously fail? Then come to our tutorial “Demystifying Memory Models Across the Computing Stack” on Saturday, June 22nd at FCRC! Please spread the word! http://check.cs.princeton.edu/tutorial.html
Tutorial on High Performance Distributed Deep Learning
Tutorial on High Performance Distributed Deep Learning: A Beginnner’s Guide
ML Benchmarking Tutorial
Interested in Machine Learning and Benchmarking? Come learn about MLPerf.org, MLModelScope, TBD, and more! The goal of the tutorial is to bring experts from the industry and academia together to shed light on the following topics to foster systematic development, reproducible evaluation, and performance analysis of deep learning artifacts. It seeks to address the following questions: What are the benchmarks that can effectively capture the scope of the ML/DL domain? Are the existing frameworks sufficient for this purpose? What are some of the industry-standard evaluation platforms or harnesses? What are the metrics for carrying out an effective comparative evaluation?
PyMTL Tutorial
PyMTL Tutorial @ ISCA’19 on Saturday, June 22nd, 2019. This tutorial will introduce the computer architecture research community to the features and capabilities of the new version of PyMTL, a next-generation Python-based hardware generation, simulation, and verification framework.
TVM Tutorial
TVM Tutorial at FCRC 2019
Tutorial on Hardware Accelerators for Deep Neural Networks
This tutorial provides a brief recap on the basics of deep neural networks and is for those who are interested in understanding how those models are mapping to hardware architectures. We will provide frameworks for understanding the design space for deep neural network accelerators including managing data movement, handling sparsity, and importance of flexibility.
Tutorial on SoC Modeling and Infrastructure
We will hold a tutorial about the techniques and tools on how to model Systems-on-a-Chip as well as how to use SCALE-SIM, a cycle-accurate timing, power/energy, memory bandwidth and trace results generating simulator for systolic-array based CNN accelerator. The tutorial will happen on June 22nd, 2:30PM to 5:30PM at the 46th ISCA conference.
Workshop on AI-assisted Design for Architecture
The 2nd International Workshop on AI-assisted Design for Architecture (AIDArc-2) in conjunction with ISCA 2019 Phoenix, Arizona, USA June 22, 2019 Recent advancements in machine learning algorithms, fueled by increased data availability and high-perforDetails…
SYSTOR 2019
SYSTOR 2019 will take place on June 3-5, at Haifa, Israel. Registration is now open: https://www.systor.org/2019/registration.html SYSTOR is a single-track conference that serves as an international platform dedicated to the broad area of systems and storage.
Workshop on ACM SIG Heritage
Workshop on ACM SIG Heritage Minneapolis, Minnesota, USA May 20-21, 2019 The Association for Computing Machinery, founded in 1947, is the oldest and largest educational and scientific society dedicated to the computing profession, and today has more thDetails…
VEE 2019
VEE 2019 Call For Participation The 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE’19) 14 April 2019 Providence, Rhode Island, United States (Co-located with ASPLOS) https://conf.researchr.org/home/vee-2019
Tutorial on Post-Moore Computing
Post-Moore Computing Tutorial in conjunction with ASPLOS 2019 Providence, RI, USA Apr 14, 2019 This tutorial will provide an overview of the new “Post-Moore” testbed hosted by Georgia Tech, the CRNCH Rogues Gallery in the Center for Research into NovelDetails…
ASPLOS 2019
This is a friendly reminder to register for ASPLOS’19. If you haven’t registered yet, there is still time! The early registration deadline for ASPLOS’19 is on March 22.
SELSE 2019
The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE includes papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Participants from industry and academia explore both current technologies and future research directions.
ISPASS 2019
ISPASS 2019 Call for Participation – Early registration and hotel deadlines on Feb. 15, 2019.
Nonvolatile Memories Workshop 2019
Registration for the 2019 Nonvolatile Memories Workshop (NVMW) is now open. The conference will be held March 10-12 in San Diego, CA. Student and postdoc travel grants are available. Please see (http://nvmw.ucsd.edu/attending) for information about attending and registration.
Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
Schedule includes 2 keynote talks, 1 invited talk and 9 paper presentations. Keynote talks by: Bill Dally (Stanford & NVIDIA), Onur Mutlu (ETH & CMU).
CGO 2019
CGO-2019 Call for Participation
HPCA 2019
2019 IEEE International Symposium on High-Performance Computer Architecture (HPCA) Washington D.C., USA February 16-20, 2019 Early registration deadline: Jan 15, 2019 Please check the Registration Page: http://hpca2019.seas.gwu.edu/registration.html ThDetails…
Workshop on Emerging Deep Learning Accelerators
In this HiPEAC 2019 workshop we aim to bring together researchers working in Machine Learning and System Architectures to discuss requirements, opportunities, challenges and next steps in developing novel approaches for accelerating deep neural networks.
MICRO 2018
The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 51st MICRO in Fukuoka, Japan.
ICCD 2018
Call for Participation – ICCD 2018
Embedded Systems Week
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), a special IoT Day, two symposia (RSP, NOCS), and hot-topic workshops and tutorials, ESWEEK presents attendees a wide range of topics unveiling the state of the art in embedded systems design and HW/SW architectures. This year F1/10 challenge is also held as a special event. Registered attendees are entitled to attend sessions of all conferences CASES, CODES+ISSS, EMSOFT, and the IoT Day. Symposia, workshops, F1/10 challenge, and tutorials require separate registration.
IISWC 2018
IEEE International Symposium on Workload Characterization (IISWC) Raleigh, North Carolina, USA September 30 – October 2, 2018 This symposium is dedicated to the understanding and characterization of workloads that run on all types of computing systems.Details…
ISLPED 2018
International Symposium on Low Power Electronics and Design (ISLPED) Bellevue, Washington July 23-35, 2018 ISLPED is the world’s premier event on low power design. It is sponsored by the IEEE Circuits and Systems Society and the ACM Special Interest GrDetails…
ANCS 2018: Student Travel Grants
The 14th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS) July 23-24, 2018 Ithaca, USA Award application deadline: June 12, 2018 We are pleased to offer a limited number of awards supporting student expenses associatDetails…
International Conference on Supercomputing
The International Conference on Supercomputing (ICS) is the premier international forum for the presentation of research results in high-performance and supercomputing. The 2018 conference will be held in Beijing, China, on June 12-15, 2018.
Workshop on Reconfigurable Acceleration in Datacenters
Dear colleagues, We sincerely invite you to register and attend the ReconfigAccel 2018 workshop: International Workshop on Reconfigurable Acceleration in Datacenters. The workshop is co-located with ICS 2018 (International Conference on Supercomputing) in Beijing, China, June 12, 2018. Please find the registration link here: http://ics2018.ict.ac.cn/#registration/ The program features i) a keynote talk by Xilinx VP Dan Gibbons: “Adaptable Computing – The Future of Acceleration with FPGAs”, ii) 7 talks from top academic research groups working on this topic, including Cornell, ETH, Peking University, Tsinghua University, and ICT, CAS, and iii) 5 talks from leading industry companies focusing on this area, including Microsoft, Alibaba, Baidu, Xilinx, and Falcon Computing. These talks will cover three major topics of reconfigurable acceleration in datacenters: Novel Accelerators and Architectures, Tools and Infrastructures, and New Advances in Machine Learning. A detailed program schedule is posted on the workshop website: http://www.openhw.org/ics2018/reconfigAccel
SYSTOR 2018
SYSTOR is a single-track conference that serves as an acclaimed international platform dedicated to the broad area of systems and storage. The SYSTOR’18 technical program features original peer-reviewed research papers, three keynotes delivered by distinguished speakers, highlight papers recently published in top-tier conferences (FAST, INFOCOM, EuroSys, VLDB, APSLOS, and USENIX Security Symposium), and a poster session. We are also proud to host a collocated meetup “Creating a work Culture that Fosters Creativity, Collaboration and Critical Thinking” featuring distinguished panelists from both industry and academia.
Tutorial: The Case for Labeled von Neumann Architecture
This tutorial will introduce a novel architecture, Labeled von Neumann Architecture (LvNA). The main idea of LvNA is to convey an application’s semantics to the hardware. With labels, LvNA can equip traditional hardware with the properties of distinguishability, isolation and prioritization. We develop a new project Labeled RISC-V, which constructs the RISC-V Rocket Chip project into LvNA. Labeled RISC-V has been already open-sourced at https://github.com/LvNA-system/labeled-RISC-V.
Workshop on AI-assisted Design for Architecture
1st Workshop on AI-assisted Design for Architecture (AIDArc) in conjunction with ISCA 2018 Los Angeles, USA June 3, 2018 (Sunday) Program: – Keynote I: Machine Learning in Computer Systems Research, Daniel A. Jiménez (TAMU) – Technical paper 1: “BeyondDetails…
ISCA 2018 Tutorials
Call for Participation for ISCA 2018 Tutorials Tutorials will be held June 2-3. Early Registration deadline will be April 16, 2018.
ISCA 2018
The 45th International Symposium on Computer Architecture (ISCA) Los Angeles, USA June 2-6, 2018 International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and research results in Computer Architecture. ISCA’18 is very pDetails…
ISCA 2018 Workshops
Call for Participation for ISCA 2018 Workshops
Workshop on Silicon Errors in Logic – System Effects 2018
The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions.
ISPASS 2018
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Belfast, Northern Ireland (UK) April 2-4, 2018. The 2018 IEEE International Symposium on Performance Analysis of Systems and Software will take place on the campus ofDetails…
ASPLOS 2018
The 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) Williamsburg, Virginia, USA March 24-28, 2018 IMPORTANT DATES: Early registration deadline: March 2, 2018 Student travel grant appliDetails…
Workshop on Grand Challenges in Computer Systems Research
It is now a time of wrenching changes in computer systems research. The community is researching an unprecedentedly broad range of topics, ranging from the small (internet of things) to the large (exascale datacenters), simultaneously addressing technology discontinuities (End of Moore’s Law and Energy Wall), new challenges in security and privacy, and the rise of artificial intelligence. It is in this context that NSF is sponsoring a community visioning workshop on Grand Challenges in Computer Systems Research on a 10-15 year horizon. This workshop will focus on architecture, operating systems, and programming systems, and be co-located with ASPLOS. The workshop will be organized around a few topics: Internet of Things and Infrastructure; Augmenting Human Abilities and AI; Security and Privacy; and Complexity Management. This Call for Participation includes the schedule.
Workshop on Reproducible and Pareto-Efficient Deep Learning
ReQuEST @ ASPLOS’18 Call for Participation
2018 Non-Volatile Memories Workshop
The 9th Annual Non-Volatile Memories Workshop (NVMW 2018) provides a unique showcase for outstanding research on solid state, non-volatile memories.
HPCA 2018 Student Travel Grants
HPCA 2018 is now offering travel support to encourage student participation.
CGO 2018
CGO 2018: Call for Participation Registration is open at http://cgo.org/cgo2018/registration/ **Early registration ends on January 11th 11:59pm, 2018 any time on earth.** **CGO 2018 is also offering travel support for students attending US or non-US universities.** For more information see: http://cgo.org/cgo2018/travel-grants/
HPCA 2018
HPCA 2018 EARLY REGISTRATION DEADLINE EXTENSION: JANUARY 15
ASPLOS 2018 Shadow PC
Call for Shadow PC Participation The 23rd International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS is organizing a shadow program committee for ASPLOS 2018. If you are interested in participating, please send an email to the shadow PC organizers: Johann Hauswald (University of Michigan, jahausw AT umich.edu) and Yunqi Zhang (University of Michigan, yunqi AT umich.edu) before July 31st, 2017. Please include a short paragraph describing your current research, areas of expertise, and publications: this will help us with selecting candidates and assigning papers for review. Feel free to reach out should you have any questions.
Webinar on NSF/Intel Partnership on Foundational Microarchitecture Research
NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) Webinar
ICCD 2017
Call for Participation for 2017 IEEE International Conference on Computer Design (ICCD) in Boston Area, MA, USA. Nov 5-8, 2017.
NOCS 2017
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Being co-located with the Embedded Systems Week 2017, NOCS 2017 will be held in Seoul, the capital of South Korea. Registration and hotel reservation are available online at http://www.esweek.org/. Please note that September 10, 2017 is the deadline for both Hotel reservation and Advance registration. Advance program is available online. Please visit http://www.arc.ics.keio.ac.jp/nocs17/ Keynote —————- Networks Off Chip: High performance Fabrics in support of the Data Center Computer Robert Zak (Intel) Panel —————- Networks-on-Chip: Past, Present and Future Panelists: – Luca Carloni (Columbia University, USA) – Nanni de Micheli (EPFL, Switzerland) – Ahmed Hemani (KTH Royal Institute of Technology, Sweden) – Vijaykrishnan Narayanan (Pennsylvania State University, USA) – Partha Pande (Washington State University, USA) – Sudhakar Yalamanchili (Georgia Tech., USA) Advance Program —————- *** Thursday October 19, 2017 *** 8:45-10:00 Keynote Networks Off Chip: High Performance Fabrics in Support of the Data Center Computer Robert Zak (Intel Corporation) 10:00-10:30 Coffee Break 10:30-12:30 Session 1: Efficient Router and NoC Architecture Minimally Buffered Deflection Routing with In-Order Delivery in a Torus Jorg Mische, Christian Mellwig, Alexander Stegmeier, Martin Frieb and Theo Ungerer (University of Augsburg) Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect Charles Effiong, Gilles Sassatelli and Abdoulaye Gamatie (LIRMM) A Novel Approach to Reduce Packet Latency Increase caused by Power Gating in Network-on-Chip Peng Wang, Sobhan Niknam (Leiden University), Zhiying Wang (National University of Defense Technology) and Todor Stefanov (Leiden University) Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling Ishan Thakkar, Sai Vineel Reddy Chittamuru and Sudeep Pasricha (Colorado State University) 12:00-01:30 Lunch 1:30-3:00 Session 2: Interconnect Architecture and Heterogeneous System (Best paper candidates session) Energy and Area Efficient Near Field Inductive Coupling: A Case study on 3D NoC Srinivasan Gopal, Sourav Das, Partha Pande and Deukhyoun Heo (Washington State University) Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer Kshitij Bhardwaj, Weiwei Jiang and Steven M. Nowick (Columbia University) BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems Amirhossein Mirhosseini (University of Michigan), Mohammad Sadrosadati, Behnaz Soltani, Hamid Sarbazi-Azad (Sharif university of Technology) and Thomas Wenisch (University of Michigan) 3:00-3:30 Coffee Break 3:30-5:30 Panel Discussion: Networks-on-Chip: Past, Present and Future Panelists: – Luca Carloni (Columbia University, USA) – Ahmed Hemani (KTH Royal Institute of Technology, Sweden) – Nanni de Micheli (EPFL, Switzerland) – Vijaykrishnan Narayanan (Pennsylvania State University, USA) – Partha Pande (Washington State University, USA) – Sudhakar Yalamanchili (Georgia Tech., USA) *** Friday October 20, 2017 *** 8:30-10:00 Special Session 1: Driving Networks from Chips to Vehicles Fault-Tolerant Mapping for CAN-based Distributed Automotive Systems Hengyi Liang, Zhilu Wang, Bowen Zheng, Qi Zhu (University of California, Riverside) JAMS: Jitter-aware Message Scheduling for FlexRay Automotive Networks Vipin Kumar Kukkala, Sudeep Pasricha (Organizer), Thomas Bradley (Colorado State University) Design with Hybrid Automotive In-Vehicle Networks Debayan Roy, Michael Balszun, Dip Goswami, Samarjit Chakraborty (TU Eindhoven) 10:00-10:30 Coffee Break 10:30-12:00 Session 3: QoS and Application Mapping Fairness-Oriented and Location-Aware NUCA for Many-Core SoC Zicong Wang, Xiaowen Chen, Chen Li and Yang Guo (National University of Defense Technology) On the Accuracy of Stochastic Delay Bound for Network on Chip Gaoming Du, Yongliang Zhang, Guanyu Liu, Zhenmin Li, Duoli Zhang and Yiming Ouyang (Hefei University of Technology) SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers Hossein Farrokhbakht, Hadi Mardani Kamali and Shaahin Hessabi (Sharif University of Technology) On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC Bing Li, Xiaohang Wang (South China University of Technology ), Amit Kumar Singh (University of Southampton) and Terrence Mak (The Chinese University of Hong Kong) 12:00-01:30 Lunch 1:30-3:00 Session 4: NoC design for 3D stacking and neural networks XYZ-Randomization using TSVs for Low-Latency Energy-Efficient 3D-NoCs Hiroshi Nakahara, Nguyen Anh Vu Doan, Ryota Yasudo and Hideharu Amano (Keio University) 3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs Biresh Joardar, Wonje Choi (Washington State University), Ryan Kim (Carnegie Mellon University), Jana Doppa, Partha Pande (Washington State University), Diana Marculescu and Radu Marculescu (Carnegie Mellon University) Rethinking NoCs for Spatial Neural Network Accelerators Hyoukjun Kwon, Ananda Samajdar and Tushar Krishna (Georgia Institute of Technology) 3:00-3:30 Coffee Break 3:30-4:50 Special Session 2: Adaptive Manycore Architectures for Big Data Computing Adaptive Manycore Architectures for Big Data Computing Janardhan Rao Doppa (Washington State University), Ryan Kim (Carnegie Mellon University), Mihailo Isakov and Michel A. Kinsy (Boston University), HyoukJun Kwon and Tushar Krishna (Georgia Institute of Technology) 4:50-5:00 Closing Remark ———————– Further information is available via: http://www.arc.ics.keio.ac.jp/nocs17/ Organizing Committee ——————– General Chairs: Axel Jantsch (Vienna University of Technology, Austria) Hiroki Matsutani (Keio University, Japan) Technical Program Chairs: Zhonghai Lu (KTH Royal Institute of Technology, Sweden) Umit Ogras (Arizona State University, USA) Special Session/Demo Chair: Paul Bogdan (University of Southern California, USA) Industry Chair: Soojung Ryu (Samsung, Korea) Finance Chair: Sudeep Pasricha (Colorado State University, USA) Publicity Chairs: Jose Flich (Universitat Politecnica de Valencia, Spain) Paul Gratz (Texas A&M University, USA) Dong Xiang (Tsinghua University, China) Web Chair: Akram Ben Ahmed (Keio University, Japan) Local Arrangements Chair: Hyung Gyu Lee (Daegu University, Korea) Steering Committee Chair: Radu Marculescu (Carnegie Mellon University, USA)
OpenPiton Tutorial
This tutorial will introduce the user to OpenPiton including how to use the framework to build different designs. OpenPiton is an open source framework designed to enable scalable architecture research prototypes from 1 core to 500 million cores. OpenPiton is the world’s first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design.
Microarchitecture Level Reliability Assessment Tutorial @ MICRO
Tutorial: Microarchitecture Level Reliability Assessment: Throughput and Accuracy Early assessment of the vulnerability of microprocessor components to hardware faults can drive effective protection decisions. Microarchitecture-level simulators are employed for such early assessments and can deliver reliability reports for a large number of hardware structures taking into consideration the masking effects of the entire stack of hardware and software layers. Statistical fault injection at the microarchitecture level is a very accurate approach which, however, may suffer from low throughput if a statistically significant assessment is required. This tutorial focuses on recent advances delivered by the Computer Architecture Lab of the University of Athens in the area of microarchitecture level reliability assessment using statistical fault injection. We present GeFIN (Gem5-based Fault Injector) a state-of-the-art microarchitecture level fault injection framework built on Gem5 simulator. GeFIN supports massive and fast injection campaigns for all different types of faults (transient, permanent, intermittent) on arbitrary combinations of several dozens of microarchitectural components modeled in Gem5. We first present the baseline Gem5 engine as well as AVF (Architectural Vulnerability Factor) and FIT (Failures in Time) measurements reported by the tool which are reports fine-grained fault effects classifications. We also present two GeFIN add-ons designed to improve the throughput of the injections campaigns but preserve the accuracy of the reliability measurements. The first add-on is a set of speed-up methods on GeFIN individual runs themselves and the second add-on is MeRLiN a fault classification approach based on dynamic instruction profiling which aims at pruning the number of faults in extremely large fault lists. Both add-ons deliver large throughput improvements (several orders of magnitude) for comprehensive (and thus statistically significant) fault injection campaigns while they preserve the reported AVF measurements. The tutorial includes measurements for different microarchitectural configurations (corresponding to different CPU models), discussion about ACE analysis and fault injection at the microarchitecture level, discussion about CPU and GPU reliability assessment at the microarchitecture level as well as comparison between microarchitecture-level and register-transfer level fault injection on a commercial CPU model.
Tutorial on Hardware Architectures for Deep Neural Networks @ MICRO
Tutorial on Hardware Architectures for Deep Neural Networks co-located with MICRO-50 Speakers: Joel Emer (Nvidia/MIT), Vivienne Sze (MIT), Yu-Hsin Chen (MIT) Deep neural networks (DNNs) are currently widely used for many AI applications including computer vision, speech recognition, robotics, etc. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, designing efficient hardware architectures for deep neural networks is an important step towards enabling the wide deployment of DNNs in AI systems. In this tutorial, we will provide an overview of DNNs, discuss the tradeoffs of the various architectures that support DNNs including CPU, GPU, FPGA and ASIC, and highlight important benchmarking/comparison metrics and design considerations. We will then describe recent techniques that reduce the computation cost of DNNs from both the hardware architecture and network algorithm perspective. Finally, we will discuss the different hardware requirements for inference and training.
Workshop on Negative Outcomes, Post-mortems, and Experiences
Workshop on Negative Outcomes, Post-mortems, and Experiences (NOPE) in conjunction with MICRO 2017 Cambridge, USA October 14, 2017 IMPORTANT DATES: Paper submission: September 27, 2017 Author notification: September 29, 2017 Camera-ready version: OctobDetails…
MICRO 2017
**MICRO-50 – Call For Participation**
Workshop on Exploiting Accelerator Diversity for Cognitive Workloads
The workshop on ‘Exploiting Accelerator Diversity for Cognitive Workloads’ will explore acceleration opportunities in existing and upcoming workflows, particularly in the cognitive domain. It will also explore the creation of a community & ecosystem around POWER9 acceleration technology for academics and industry practitioners. This workshop is co-located with the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-2017).
IISWC 2017
2017 IEEE International Symposium on Workload Characterization (IISWC) Seattle, WA, USA Oct 1-3, 2017 IISWC provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge rDetails…
PACT 2017
PACT’2017 – Call for Participation – The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest. We invite attendees to register for our exciting program this year consisting of many informative workshops/tutorials, leading industry keynotes and conference papers and posters.
Tutorial for Learning and Using the Intel Xeon with Integrated FPGA
This full day tutorial will cover the architecture and programming model of the Intel© Xeon© with Integrated FPGA. This reconfigurable hardware has an integrated host processor with memory coherency between the Intel© Xeon© processor and the FPGA providing a heterogeneous compute solution for workload optimizations. With a simplified programming model (support for virtual addressing and data caching) the Intel Xeon with integrated FPGA enables new classes of algorithms for acceleration.
ISLPED 2017
The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications.
ACACES 2017
The ACACES Summer School is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture, compilation and embedded systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. A distinguishing feature of this Summer School is its broad scope ranging from low level technological issues to advanced compilation techniques and entrepreneurship. In the design of modern computer systems one has to be knowledgeable about architecture as well as about the quality of the code, and how to improve it. This summer school offers the ideal mix of the two worlds, both at the entry level and at the most advanced level.
Workshop on Trends In Machine-Learning
Workshop on Trends In Machine-Learning: Perspective from ML Research and Industry in conjunction with ISCA 2017 Toronto, Canada June 25, 2017 Machine-Learning has now become a pervasive tool used throughout the industry. This trend, combined with the pDetails…
Why Memory Consistency Models Matter… And tools for analyzing and verifying them (ISCA Tutorial)
Tutorial on Memory Consistency Model basics, and full-stack tools to analyze and verify them.
ISCA 2017
The 44th International Symposium on Computer Architecture (ISCA) Toronto, Canada June 24-28, 2017 CONFERENCE SCHEDULE: Workshops and Tutorials: Saturday, June 24 – 1st International Workshop on Architecture for Graph Processing – 7th Workshop on ArchitDetails…
Tutorial on Hardware Architectures for Deep Neural Networks
Tutorial on Hardware Architectures for Deep Neural Networks Speakers: Joel Emer (Nvidia/MIT), Vivienne Sze (MIT), Yu-Hsin Chen (MIT) Deep neural networks (DNNs) are currently widely used for many AI applications including computer vision, speech recognition, robotics, etc. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, designing efficient hardware architectures for deep neural networks is an important step towards enabling the wide deployment of DNNs in AI systems. In this tutorial, we will provide an overview of DNNs, discuss the tradeoffs of the various architectures that support DNNs including CPU, GPU, FPGA and ASIC, and highlight important benchmarking/comparison metrics and design considerations. We will then describe recent techniques that reduce the computation cost of DNNs from both the hardware architecture and network algorithm perspective. Finally, we will discuss the different hardware requirements for inference and training. More info at http://eyeriss.mit.edu/tutorial.html
HOST 2017
You are cordially invited to the 10th annual IEEE International Symposium on Hardware Oriented Security and Trust (HOST). HOST 2017 will feature a rich one-week program. Major highlights include: 1. This year marks the 10th anniversary of HOST. 2. ForDetails…
FCCM 2017
The IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware.
ISPASS 2017
2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Santa Rosa, Sonoma County, California April 24-25, 2017 IMPORTANT DATES: Student Travel Grant application deadline: April 3, 2017 Early Registration Deadline: ApDetails…
Cyber-Physical Systems Week
You are cordially invited to participate in the 10th Anniversary Edition of Cyber-Physical Systems Week (CPS Week). CPS Week is the premier event on Cyber-Physical Systems research. It brings together five top conferences (HSCC, ICCPS, IoTDI, IPSN, RTAS) and eleven workshops on cyber-physical systems research, in addition to competitions and various exhibitions from both industry and academia.
WAX 2017
WAX, the workshop on approximate computing, will be co-located again with ASPLOS this year. WAX is a venue for discussion computer systems that trade off accuracy for efficiency in all forms.
ASPLOS 2017
The 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2017) Xi’an, China, April 8–12, 2017 ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecturDetails…
Tutorial on Quantum Computing
This tutorial will introduce the basic notions of quantum computing and will address the main challenges when building a large-scale quantum computer. The tutorial will provide hands-on exercises based on the QX simulator platform and will allow participants to understand what quantum circuits and quantum gates are.
Learning gem5 Tutorial
We will be holding a Learning gem5 Tutorial and a gem5 coding sprint at HPCA 2017 on February 5th in Austin, TX. The morning will consist of a “Learning gem5” half-day course. In the afternoon, we invite all gem5 developers senior, junior, and new developers to a “coding sprint.”
HPCA 2017 (early registration deadline: Jan 11)
The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.
CGO 2017
The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.
IISWC 2016
IISWC provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on understanding and characterization of workloads that run on all types of computing systems. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them.
Workshop on In-Memory and In-Storage Computing with Emerging Technologies
Workshop on In-Memory and In-Storage Computing with Emerging Technologies invites you to share your research and creative endeavors with your colleagues. Our program features 6 selected papers on a variety of subjects including computer architecture and algorithms based on resistive memory technologies such as memristors, RRAM, PCM, 3D Xpoint, STT-MRAM and others. Authors will present a wide range of potential applications including digital computing, non-volatile storage with processing capabilities, neuromorphic computing, etc. We will further discuss the use of emerging technologies as an enabler of the next generation of new architectures that address the major shortcomings of today’s conventional high-performance computing such as latency, energy, power efficiency and scalability.
NOCS 2016
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.
MobiTools Tutorial Co-located with ISCA 2016
The tutorial is a step to overcome the increasing barrier of entry for conducting mobile computer architecture research. We present a series of tools and infrastructures that enable computer system and architecture research in the mobile computing space. The tutorial will span three key components of mobile computing: software, hardware, and end-users.
OpenPiton Tutorial
This tutorial will introduce the user to OpenPiton including how to use the framework to build different designs. The tutorial will introduce the verification framework (Verilog simulation), how to synthesize an OpenPiton processor for a Xilinx FPGA board, it will demonstrate booting Linux on an FPGA version of OpenPiton, it will familiarize users with how to use the OpenPiton framework to target an ASIC tapeout, and it will show users how to configure and extend the OpenPiton architecture to enable architecture research. This tutorial will be hands-on so please bring a laptop.
ACM Workshop on Oral History
Applications are invited to a 1.5 day oral history workshop, to be held Thursday and Friday, May 12-13, 2016 at the University of North Carolina at Chapel Hill, North Carolina. The workshop will be led by Mary Marshall Clark, director of the Columbia Center for Oral History (CCOH)
ISPASS 2016
EEE International Symposium on Performance Analysis of Systems and Software. The focus is on performance-related problems, solutions, methods and tools for software and system performance and power analysis and optimisation.
ASPLOS 2016
The Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2016)
SELSE 2016
The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
HPCA 2016
The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. HPCA-22 will be held in conjunction with the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP-2016) and the 14th International Symposium on Code Generation and Optimization (CGO-2016).
HiPEAC 2016 Conference
The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems.
CWWMCA 2015
The CWWMCA Workshop brings together women and under-represented minorities in academia, industry, and government to promote the recruitment, retention and progression of women and under-represented groups with research interests in computer architecture.
Tutorial on Building Online Power Models from Real Data
In this hands-on, interactive tutorial, you will learn how to efficiently build accurate, run-time power models using real hardware platforms using a specially built software tool. Starting from the basics of how power is consumed in a modern system-on-chip through static and dynamic power in the underlying transistors, we show how activity, voltage and frequency affect the power consumption.
Tutorial on Dynamic Binary Instrumentation of Application, OS Kernel, Driver and BIOS
We introduce the Intel® Simulation and Analysis Engine (Intel® SAE) — a framework for full-system instruction-level instrumentation of “ring 0” (privileged) and “ring 3” (user-level) code behavior. When plugged-in to a Wind River® Simics Virtual Platform, Intel® SAE boots native operating systems (e.g. Linux and Windows, as well as Android), and runs unmodified binaries while facilitating flexible and customizable instruction-level instrumentation of everything executing on the CPU, i.e. BIOS, kernel, drivers and kernel and user-space processes.
IISWC 2015
IISWC is the only symposium of its kind anywhere. If you are interested at all with what computing workloads really look like today, IISWC is where you can get answers.
Hot Interconnects 2015
Hot Interconnects (HotI) is the premier international forum for researchers and developers of state- of-the-art hardware and software architectures and implementations for interconnection networks of all scales, ranging from multi-core on-chip interconnects to those within systems, clusters, data centers, and clouds. This yearly conference is attended by leaders in industry and academia, creating a wealth of opportunities to interact with individuals at the forefront of this field.
NAS 2015
NAS provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies.
ASAP 2015
The 26th IEEE International Conference on Application-specific Systems, Architectures and Processors 2015 (ASAP 2015) takes place July 27-29, 2015 at the University of Toronto in Toronto, Canada. ASAP is a premiere IEEE conference covering all aspects of application-specific computing, including systems, architectures, processors, and design methodologies/tools.
ISLPED 2015
ISLPED is the world’s premier event on low power design. It is sponsored by the IEEE Circuits and Systems Society and the ACM Special Interest Group on Design Automation.
ACM SIGMETRICS 2015
ACM SIGMETRICS is the flagship conference of the ACM special interest group for the computer systems performance evaluation community.
Tutorial on IO virtualization
Virtualizing IO through Memory Management Unit (IOMMU): Use Cases and Internals of IOMMU
Workshop on Architectural Research Prototyping
Building prototype systems can be one of the best ways to validate assumptions, gain intuition about practical design issues, and provide platforms for future software research. While the research ideas behind these prototypes can be published in top-tier conferences, there are not many venues suitable for focusing on the actual prototype itself. At the same time, building an FPGA, ASIC, or full-custom computer architecture prototype is a non-trivial endeavor and requires a significant financial and time commitment. This workshop is intended as a forum for the builders in our community to share their practical on-the-ground experiences, to provide a status update on their progress, and to convey insights for those considering prototyping their ideas.
Workshop on Computer Architecture Research Directions
CARD 2015 presents three mini-panels consisting of three experts in the field, two as panelists and the third as a moderator/panelist. The purpose of this workshop is to serve as a forum in which experts in each field can debate the state of the field and future directions. The format is designed to quickly focus on areas of disagreement, rather than expounding on areas of agreement which, presumably, have ceased to be controversial, at least between the two panelists. The mini-panels are intended to help clarify the open issues of each topic and to discuss those open issues. The hope is that the workshop will be useful to a diverse audience from a graduate student looking for good thesis topic areas to a senior researcher who wants to hear the opinions of other area experts.
ISCA 2015
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. ISCA is sponsored by ACM SIGARCH and IEEE Computer Society TCCA.
ISCA 2015
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. This year ISCA will be held in the Oregon Convention Center in Portland, Oregon during June 13-17, 2015. Sponsored by ACM SIGARCH and IEEE TCCA.
Workshop on Approximate Computing Across the Stack
WAX 2015 is a workshop on approximate computing, a research direction that asks how computer systems can be made better, faster, more efficient, and less complex by relaxing the requirement that they be exactly correct. Approximation arises from sources as diverse as sensors, machine learning algorithms, and big data applications. Approximate systems raise questions from across the system stack, from circuits to applications. WAX is avenue for discussion, debate, and brainstorming on all of these topics.
ICS 2015
ICS is the premier international forum for the presentation of research results in high-performance computing systems.
ANCS 2015
ANCS is the premier forum for presenting and discussing original research that explores the relationship between the algorithms and architectures of data communication networks and the hardware and software elements from which these networks are built. This includes both experimental and theoretical analysis. To recognize and foster the increasing importance of research into the co-design of computer and network systems, the conference also places an emphasis on systems issues arising from the interaction of computer and network architectures.
ISPASS 2015
2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
ASPLOS 2015
20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
ASPLOS 2015
ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking, as well as applications and user interfaces.
4th Annual Non-Volatile Memories Workshop
The 4th Annual Non-Volatile Memories Workshop (NVMW 2013) provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated”program that includes presentations on a wide range of topics spanning devices, data encoding, systems architecture, and applications.
Non-Volatile Memory Workshop
NVMW provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated” program that includes presentations on devices, data encoding, systems architecture, and applications related to these exciting new data storage technologies.
HPCA 2015
HPCA is a top-tier computer architecture conference, and will have many industry and academic participants.
CGO 2015
CGO brings together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues.
HPCA 2015
HPCA is a premier annual computer architecture conference sponsored by the Computer Society of the Institute of Electrical and Electronics Engineers (IEEE CS). It will bring together researchers, academics, and industrial engineers from all over the world.
HPCA 2015
HPCA is a premier annual computer architecture conference sponsored by the Computer Society of the Institute of Electrical and Electronics Engineers (IEEE CS). It will bring together researchers, academics, and industrial engineers from all over the world.
HiPEAC 2015
The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems. Associated workshops, tutorials, special sessions, several large poster sessions and an industrial exhibition will run in parallel with the conference. The three day event attracts about 500 delegates each year.
HiPEAC 2015
10th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC)
RISC-V Workshop and Bootcamp
RISC-V (pronounced “risk-5”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley, but has been made freely available open-source under the BSD license for anyone to use.
Top Picks community input
IEEE Micro will publish its yearly Micro’s Top Picks from Computer Architecture Conferences as its May / June 2015 issue. This issue collects some of this year’s most significant research papers in computer architecture based on novelty and potential for long-term impact. The community input website will be open between Dec 18, 2014 and Jan 17, 2015. Reviews will be anonymous to the authors but they will not be anonymous to the selection committee.
MICRO-47
The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems.
IISWC 2014
This symposium is dedicated to the understanding and characterization of workloads that run on all types of computing systems. New applications and programming paradigms continue to emerge rapidly as the diversity and performance of computers increase. On one hand, improvements in computing technology are usually based on a solid understanding and analysis of existing workloads. On the other hand, computing workloads evolve and change with advances in microarchitecture, compilers, programming languages, and networking communication technologies. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them. This symposium will focus on characterizing and understanding emerging applications in consumer, commercial and scientific computing.
SPAA 2014
26th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2014)
D43D: International Workshop on Design for 3D Silicon Integration
3D IC is emerging as a promising approach to extend Moore’s law, overcome pin bandwidth limitations, and improve digital platform density and cost beyond a single chip. 3D IC as a technology, however, also introduces a number of key design, methodological, implementation and technological challenges that must be overcome to become practical and cost-effective.
ASAP 2014
The 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014)
ISCA-41
The 41st International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture.
ISCA 2014
ISCA 2014 The 41st International Symposium on Computer Architecture
ICS 2014
ICS is the premier international forum for the presentation of research results in high-performance computing systems.
Computing Frontiers’14
Computing Frontiers is a gathering for people to share and discuss such work, focusing on a wide spectrum of advanced technologies and radically new solutions relevant to the development of the whole spectrum of computer systems, from embedded to high-performance computing.
4th Workshop on Systems for Future Multicore Architectures (SFMA’14)
Future multi-core architectures will present a variety of challenges for system developers, such as non-cache-coherent memory, heterogeneous processing cores and the exploitation of novel architectural features. SFMA ’14 is a forum for researchers in the architecture, operating systems, language runtime and virtual machine communities to present and discuss their experiences with the new generation of highly-parallel hardware.
ISPASS 2014
The 2014 IEEE International Symposium on Performance Analysis of Systems and Software is sponsored by the IEEE Computer Society’s Technical Committee on Internet, Technical Committee on Computer Architecture, and Technical Committee on Microprogramming and Microarchitecture.
5th Non-Volatile Memories Workshop
The 5th Annual Non-Volatile Memories Workshop (NVMW 2014) provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated” program that includes includes presentations on a wide range of topics spanning devices, data encoding, systems architecture, and applications:
Rigorous and Practical Server Design Evaluation tutorial at ASPLOS 2014
The emergence of cloud computing as a dominant computing platform highlights the need for practical and rigorous architectural evaluation of server systems. Such evaluation mandates the use of a variety of real-world server workloads, all of which are radically different from traditional desktop and scientific benchmarks.
Rigorous and Practical Server Design Evaluation – tutorial at ASPLOS 2014
The emergence of cloud computing as a dominant computing platform highlights the need for practical and rigorous architectural evaluation of server systems. Such evaluation mandates the use of a variety of real-world server workloads, all of which are radically different from traditional desktop and scientific benchmarks. Unfortunately, deep and complex software stacks of both conventional (e.g., OLTP, DSS) and emerging scale-out (e.g., Media Streaming, Web Search) server workloads make the evaluation process even harder and slower, postponing the adoption of realistic server benchmarks within the architectural community.
ASPLOS 2014
19th International Conference on Architectural Support for Programming Languages and Operating Systems
ASPLOS 2014
ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, and operating systems and networking. The program covers cross-cutting research spanning mobile systems to data centers, targeting diverse goals such as performance, energy efficiency, resiliency, and security.
ASPLOS 2014
ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, and operating systems and networking. The program covers cross-cutting research spanning mobile systems to data centers, targeting diverse goals such as performance, energy efficiency, resiliency, and security.
CGO 2014
The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues.
HPCA-20
The 20th IEEE International Symposium on High-Performance Computer Architecture
ADAPT 2014 @ HiPEAC 2014
ADAPT: 4th Workshop on Adaptive Self-tuning Computing Systems
IEEE ICPADS 2013
Established in 1992, ICPADS has been a major international forum in the parallel and distributed systems area. ICPADS 2013 will be held in Seoul, December 15-18, 2013. Seoul is a city of various culture and variation. There is a wide range of modern and fusion culture of the West and the East, along with cutting edge technology. The conference venue, COEX convention center is located at Gangnam district that is famous for a song, Gangnam Style, by Korean singer Psy. The conference provides an international forum for scientists, engineers, and users to exchange and share their experiences, ideas, and latest results on all aspects of parallel and distributed systems.
MICRO 2013
The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers — we aim to continue and strengthen this longstanding tradition at the 46th MICRO in Davis
SPAA 2013
25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)
IEEE NAS 2013
The 8th IEEE International Conference on Networking, Architecture, and Storage (NAS 2013), June 17 – July 19, 2013, Xi’an, China, will serve as an international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2013 will expose participants to the most recent developments in the interdisciplinary areas.
ACACES 2013
The ACACES Summer School is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture, compilation and embedded systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. A distinguishing feature of this Summer School is its broad scope ranging from low level technological issues to advanced compilation techniques. In the design of modern computer systems one has to be knowledgeable about architecture as well as about the quality of the code, and how to improve it. This summer school offers the ideal mix of the two worlds, both at the entry level and at the most advanced level.
SYSTOR 2013
SYSTOR provides a forum for interaction across the systems and storage community: international, academic, and industrial, for both students and more established members. The program include high-quality experimental and practical research papers encompassing all aspects of computer systems, with an emphasis on storage.
CloudSuite 2.0 on Flexus Tutorial at ISCA 2013
The emergence of cloud computing as a dominant computing platform highlights the need for a common architectural evaluation basis of cloud server systems. CloudSuite is an on-going effort towards this end, aimed at providing a contemporary suite of benchmarks that represent popular scale-out cloud applications commonly found in today’s datacenters.
GPUWattch at ISCA 2013
General-purpose GPUs (GPGPUs) are becoming prevalent in mainstream computing, and performance per watt has emerged as a more crucial evaluation metric than peak performance. As such, GPU architects require robust tools that will enable them to quickly explore new ways to optimize GPGPUs for energy efficiency. We propose a new GPGPU power model that is configurable, capable of cycle-level calculations, and carefully validated against real hardware measurements.
PACT 2013 – ACM Student Research Competition
The 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) invites participation in the ACM Student Research Competition (SRC).
ISPASS 2013 — Workshops and Tutorials
ISPASS 2013 — Workshops and Tutorials
ISPASS 2013 – Tutorial on Modeling Exascale Applications with SST/macro and Eiger
This tutorial will present attendees with the techniques and methodologies to leverage the SST/macro simulator and the Eiger performance modeling framework for modeling large scale applications on upcoming supercomputer hardware.
NOCS-13, Extended Registration Deadline
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip and chip-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation.
ISPASS 2013
The IEEE International Symposium on Performance Analysis of Systems and Software provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software.
SELSE 2013
The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes.
ASPLOS 2013 Tutorial — Using Queuing Theory to Model Data Center Systems
Recently, there has been an explosive growth in Internet services, greatly increasing the importance of data center systems. Applications served from ìthe cloudî are driving data center growth and quickly overtaking traditional workstations. Although there are many analytic and simulation tools for evaluating components of desktop and server architectures in detail, scalable modeling tools are noticeably missing.
HPCA-19
The program committee has put together a strong technical program with a record number of accepted papers (51 regular papers + 4 industrial session papers). We also have scheduled five tutorials and four workshops. We look forward to your participation in this important event.
PPoPP 2013
PPoPP is a forum for leading work on all aspects of parallel programming, including foundational and theoretical aspects, techniques, languages, compilers, runtime systems, tools, and practical experiences. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multithreaded, heterogeneous, clustered systems, distributed systems, grids, clouds, and large scale machines).
ADAPT 2013 @ HiPEAC 2013
ADAPT: 3rd International Workshop on Adaptive Self-tuning Computing Systems
IISWC 2012
IISWC is the premier international conference dedicated to the understanding and characterization of workloads that run on all types of computing systems. Whether they are PDAs/smartphones at the low end or supercomputers at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them. IISWC 2012 will focus on characterizing and understanding these modern computer applications.
ANCS 2012
ANCS is a systems-oriented research conference, presenting original work that explores the relationship between the architecture of modern computer networks and the architecture of the individual hardware and software elements from which these networks are built. This year’s conference emphasizes in its paper selection research on computer and network systems that provide the foundations of emerging network technologies and the future Internet.
ICCD 2012
The 2012 edition of the ICCD conference marks its 30th anniversary, where special sessions, keynotes, and other events will commemorate this milestone. ICCD is proud to be one of the venues with the longest tradition in the area.
PACT-21 (Hotel reservation deadline – August 30, 2012)
International Conference on Parallel Architecture and Compilation Technologies (PACT-21)
ISPASS 2023 Student Travel Grants
ISPASS 2023 is now offering travel support to encourage student participation at the conference. Applications and the grant amount will be decided on a case-by-case basis (i.e., funding is NOT guaranteed). All undergraduate and graduate students intereDetails…