DSL-Based Hardware Generation (Calyx) Tutorial @ FCRC’23

In the last four decades, the easiest way to improve performance of programs has been to simply wait; processor and process scaling took care of the rest. Sadly, Moore’s law is over, there are no free lunches left, and everyone at the table is desperate. The only way forward is to build specialized hardware accelerators, that can be customized to the needs of the application.

So how, then, does an enterprising performance hound like yourself build an accelerator? Teach yourself a hardware design language? Stare at inscrutable errors for weeks? Just convert everything into a matrix multiply? No, thank you.

Welcome to the DSL-based Hardware Generation tutorial at FCRC 2023. We’ll show you how to stay within the comforts of your domain specific language (DSL) and turn programs written in your language into accelerated hardware designs using the Calyx compiler infrastructure. Your performance graphs will be more up and more to the right than ever before!