Tutorial on Methods for Characterization and Analysis of Voltage Margins in Multicore Processors
May 24, 2019
Tutorial on Methods for Characterization and Analysis of Voltage Margins in Multicore Processors
in conjunction with ISCA 2019
Phoenix, AZ, USA
June 23, 2019
Conservative design margins in modern multicore CPU chips aim to guarantee correct execution of the software layers of computing system under various operating conditions, such as worst-case voltage noise (Ldi/dt), and accounting for the inherent variability among different cores of the same CPU chip, among different manufactured chips and among different workloads. However, guard-banding the main operational parameters of CPU chips (voltage, frequency), leads to limited energy efficiency.
In this tutorial, we will present recent methods and studies on design-time voltage-margins characterization and identification in modern multicore CPUs; such methods aim to improve energy efficiency while guaranteeing the correctness of software execution.
– We will discuss key power-delivery-network (PDN) challenges and present an on-chip dedicated circuitry for PDN voltage noise characterization. The presentation will include various analysis conducted with real hardware using this circuitry for characterizing voltage noise caused by Ldi/dt viruses, system-call intensive benchmarks and scan-debug activity.
– We will present the main challenges and how they can be addressed for the characterization and identification of different types of variability of modern multicore CPUs (across cores, across chips and across workloads) and to analyze the system behavior in scaled conditions (what types of malfunctions are observed). Both single-thread and multi-thread workloads will be discussed.
– We will present the main challenges and how they can be addressed for the characterization and identification of different types of variability of modern multicore CPUs (across cores, across chips and across workloads) and to analyze the system behavior in scaled conditions (what types of malfunctions are observed). Both single-thread and multi-thread workloads will be discussed.
– We will present a novel non-intrusive, zero-overhead, cross-platform approach for post-silicon dI/dt voltage noise monitoring based on sensing CPU electromagnetic emanations using an antenna and a spectrum analyzer. The approach is based on the observation that high amplitude electromagnetic emanations are correlated with high voltage noise. We leverage this observation to automatically generate voltage noise (dI/dt) stress tests and measure PDN resonance frequency.
– The tutorial analysis is based on real system measurements using client chips as well as on different multicore server CPU chips mainly based on ARMv8 architecture (such as ARM Cortex-A72 and Cortex-A53 CPUs, AppliedMicro’s – now Ampere Computing – multicore X-Gene 2 and X-Gene 3 CPUs). Discussion and comparison among the implementations and also with different architectures (mainly Intel and AMD x86 multicore CPU chips) will also take place.
The purpose of the tutorial is to summarize recent characterization and exploitation findings on multicore CPUs in server machines, emphasize on the potential of energy saving through identification and exploitation of design margins and to discuss our reports and findings to other machines similarly studied in the past.