by SIGARCH Information Director on Apr 28, 2018 |

Call for Participation:

Tutorial: The Case for Labeled von Neumann Architecture

June 3, 2018 in Los Angeles
URL: http://sdc.ict.ac.cn/isca2018-tutorial

Tutorial on the Case for Labeled von Neumann Architecture
in conjunction with ISCA’18
Los Angeles, USA
June 3, 2018

Conventional instruction set architecture (ISA) defines the functional abstraction between software and hardware. Contemporary hardware design focuses on two goals. One is to implement ISA correctly to support the running of applications. Another is to optimize the datapath to make applications run faster.

However, uncertainty becomes a new problem after the emergence of multi-core architecture. One example is that, uncertainty reduces applications’ quality of services (QoS) in data centers. Therefore, contemporary data centers are confronting with challenges in managing the trade-offs between resource utilization and applications’ QoS. Another example is that, multi-core is usually disabled in aviation areas to avoid uncertainty. To make better use of the wasted computing resources, uncertainty is the critical problem to address.

To actually reduce uncertainty, as suggested in the community white paper “21st Century Computer Architecture”, computer architecture needs to provide new, higher-level interfaces beyond a conventional ISA to convey an application’s semantics to the hardware. After that, hardware can leverage such semantics to manage share resources in a more predictable way.

In this tutorial, we will present these challenges first. And then we will introduce a novel architecture, Labeled von Neumann Architecture (LvNA), to convey the software semantics down to hardware. The main idea of LvNA is to enforce distinguishability, isolation and prioritization (DIP properties) to hardware by labels. Based on the concept of LvNA, we design policies for different kinds of resources. Moreover, we will show that the principle of LvNA can also be applied to managing storage resources in terms of Flash-based Solid State Drives (SSD). To verify these ideas, we will also demonstrate our FPGA prototype, Labeled RISC-V, and apply the software-hardware co-design polices on it to present the evaluation.

Labeled RISC-V has already been open-sourced at https://github.com/LvNA-system/labeled-RISC-V.