I am broadly interested in designing efficient computer systems, and more recently, in designing energy-efficient processor and memory abstractions for datacenters.

I am a PhD candidate at the University of Illinois at Urbana-Champaign. My advisor is Prof Sarita Adve. My research interests include Error-Efficient Computing, Approximate Computing, Hardware Resiliency and Software Testing. The overarching theme of my dissertation work is enabling reliable, low-cost and efficient computing by allowing controlled errors in the system. My work aims to explore such opportunities in emerging workloads and build an ecosystem to formalize and automate the application of error-efficient computing techniques. I am among the young researchers selected to participate in the 2018 Heidelberg Laureate Forum.

Before joining UIUC, I was a CPU/Silicon validation engineer at Intel for five years, where I won a divisional award for key contributions in validating new industry standard CPU features. Prior to that I worked for 1.5 years at Qualcomm on the architectural verification of the Snapdragon processor. I completed my MS in ECE from North Carolina State University. My undergraduate degree, in Electrical Engineering, is from the University of Madras in India.

I am a PhD candidate in the Electrical and Computer Engineering department at Carnegie Mellon and a member of the ABSTRACT research group led by Professor Brandon Lucia. My research interests include computer architecture and hardware/software codesign for resource constrained, embedded devices. My current research focuses on programming and execution models for intermittently powered, energy harvesting devices.

Vijayalakshmi Saravanan received her Ph.D. in Computer Science and Engineering from VIT University, India under Erasmus Mundus Fellowship (EURECA) as research exchange student at Mälardalen University, Sweden and visiting researcher at Ryerson University, Canada. She is currently an Assistant Professor in Practice at University of Texas, San Antonio (UTSA) in the department of Computer Science. Prior to this, she was a Postdoctoral Associate at UB (University at Buffalo), The State University of New York, USA and University of Waterloo, Canada under the prestigious “Schlumberger Faculty for the Future” Fellowship award (2015-2017). She is having 10 years of teaching experience in two premier Universities VIT and Amrita Vishwa Vidyapeetham, India. Dr. Saravanan has published many technical articles in scholarly international journal and conferences. She is serving as technical reviewer and program committee member for reputed conference & journals such as GHC, SIGCSE and Springer. Her research interests include Power-Aware Processor Design, Big Data, IoT and Computer Architecture. She is a Senior Member of IEEE & ACM, CSI, Ex-Chair for IEEE-WIE VIT affinity group, India (2009-2015), NPA (National Postdoctoral Association) Annual Meetings committee, Workshop/IIA Co-Chair (2017-2018) Poster committee Co-chair (2018-2019) and a Board member of N2WOMEN (Networking Networking Women).