Yasuko Eckert is a Sr. Member of Technical Staff at AMD Research and an IEEE Senior Member. She received her M.S. and Ph.D. from the University of Wisconsin-Madison in 2007 and 2011, respectively. She received her B.S. from the University of Texas at Austin in 2004. Her research interests include SoC- and package-level architectural optimizations, 3D integration, energy-efficient computing, and microarchitecture designs. She is currently serving as the Tutorial/Workshop Co-chair of the 51st International Symposium on Microarchitecture, as well as an Associate Editor of IEEE Transactions on Multi-Scale Computing Systems (TMSCS). She has served on the Technical Program Committees of MICRO, HPCA, PACT, ISLPED, and ICCD. She holds more than 25 U.S. patents.

I recently finished my Ph.D.

My research interest is in computer architecture.

My research interest lies in the areas of computer architecture and hardware security, with a focus on defenses against transient execution attacks and cache-based side channel attacks.

I am a third-year PhD student in Electrical and Computer Engineering interested in new and niche logic families for high-performance computing purposes, including temporal-based encoding (Race Logic), and exploring superconducting architectural and circuit design trade-offs between area, energy, and tolerance to variability. I have co-authored several papers at ISCA and ASPLOS on novel logic paradigms applied to superconducting technologies. I am currently pursuing several projects, including new neuromorphic gates in superconducting electronics, and new fan-out techniques for the same technology. I have a diverse background ranging from instrumentation and testing in High-Energy Physics to embedded development in the health and wellness industry, and I received my undergraduate degree in Electrical Engineering from University of California, Santa Cruz. If you would like to hear about my research, please reach out!