I am interested in parallel and heterogeneous architectures and application-specific accelerators, and how we can design and program them to continue improving application performance and efficiency in the face of limits to frequency and power scaling.

I am a research scholar in the Electrical Engineering and Computer Science department at University of California, Irvine advised by Prof. Nader Bagherzadeh. I am interested lie in Accelerator based architecture, memory systems, multicore and parallel computing, and heterogeneous architectures. Currently, I am working on mitigating memory bottleneck in deep neural networks (DNN) accelerator based architectures.

I am a 2nd year PhD. student in the Department of Computer Science and Engineering at University at Buffalo. I am working under Dr. Ramalingam Sridhar. My research aims at improving the performance and energy efficiency of systems used for data intensive Machine Learning applications.

Server memory management is an evolving and challenging area. With growing memory capacity installed per machine and increasing memory DIMM costs, data center planners are facing with huge increase in memory TCO. A plausible direction is to categorize memory accesses by required service level objective (SLO) with the end goal to map lower SLO request to cheaper but low quality memory resource, while using expensive, highest quality memory resource for most critical application request. I work in Linux server memory management to categorize memory access transparent to the user space.