I'm a Ph.D. student at UT Austin working with Dr. Calvin Lin. Broadly, I'm interested in microarchitectural prediction for memory systems performance and in rethinking the hardware/software interface in light of modern performance, programmability, and security challenges. I'm also interested in computer architecture education. Before coming to UT, I was a CS and EE lecturer at Texas State University, and early in my career I was a hardware verification engineer at Arm.

Broadly speaking, I'm interested in computer architecture, particularly parallel systems. Prior work has included workload characterization of parallel applications and memory systems in traditional multiprocessor systems and GPUs and correctness in IoT systems.

I'm a PhD student researching microarchitectural security and side-channel attacks in the CoreSec group at the IAIK, Graz University of Technology. Developing microarchitectural attacks and countermeasures has exposed me to many subfields of computer architecture. I'm particularly interested in ISA design and instruction decoding, the 'conflict' between energy efficiency and security, and whether we can rearchitect the CPU and the memory subsystem to reduce this conflict.

Amila received her Bachelor's and Master's Degrees from the University of Sarajevo in Electrical Engineering within Computer Science and Informatics Department in 2006, 2009, respectively. In academic year 2007/2008 she received Fulbright Visiting Student Award and joined Embedded Systems and Architectures Lab at University California, Riverside as Junior Researcher. In 2010, she spent 1 month at Faculty of Electrical Engineering, University of Ljubljana as a visiting academic. Then, she received MEXT scholarship in 2010 and spend 3 and half years in beautiful Tokyo, where she completed her Ph.D. at Keio University in 2013.

Her primary area of interest is Computer Architecture, including Reconfigurable Architectures, High Performance Computing and Heterogeneous Computing. Her past research mainly focused on finding new ways to accelerate compute-intensive parts of an algorithm by means of offloading it to an FPGA. The challenge is to take advantage of knowledge about an architecture and adapt the algorithm to the architecture rather than the other way around. Her PhD research focused on developing architectures and methodologies that help to reduce the execution time of Cyclic Redundancy Check algorithms, particularly those implemented using FPGAs, and iSCSI protocol implementation.

In recent years, she has expanded her research to include Digital Signal Processing, Computer Vision, Image Segmentation, Machine Learning to name a few.