Mitali is a PhD student at Advanced Multicore Systems (AMS) lab, IIIT Delhi. She holds a gold medal in both Bachelor’s and Master's degrees. Her research interests include heterogeneous systems architectures and hardware security. She also works on designing efficient communication platforms for heterogeneous multi-core systems. She is currently focusing on design space optimization and security analysis of accelerator-rich heterogeneous system-on-chips (ArSoCs). Her recent works on energy-optimization of ArSoCs and SoC security were published in premier journals like TODAES'20 and TETC'21. She has published 1 book chapter and contributed to research works published in conferences including ASAP'18, ISCAS'18, ISVLSI'18, IGSC'18, ISCAS'20. She has experience of almost a year in academia as a lecturer and a research associate.

Amila received her Bachelor's and Master's Degrees from the University of Sarajevo in Electrical Engineering within Computer Science and Informatics Department in 2006, 2009, respectively. In academic year 2007/2008 she received Fulbright Visiting Student Award and joined Embedded Systems and Architectures Lab at University California, Riverside as Junior Researcher. In 2010, she spent 1 month at Faculty of Electrical Engineering, University of Ljubljana as a visiting academic. Then, she received MEXT scholarship in 2010 and spend 3 and half years in beautiful Tokyo, where she completed her Ph.D. at Keio University in 2013.

Her primary area of interest is Computer Architecture, including Reconfigurable Architectures, High Performance Computing and Heterogeneous Computing. Her past research mainly focused on finding new ways to accelerate compute-intensive parts of an algorithm by means of offloading it to an FPGA. The challenge is to take advantage of knowledge about an architecture and adapt the algorithm to the architecture rather than the other way around. Her PhD research focused on developing architectures and methodologies that help to reduce the execution time of Cyclic Redundancy Check algorithms, particularly those implemented using FPGAs, and iSCSI protocol implementation.

In recent years, she has expanded her research to include Digital Signal Processing, Computer Vision, Image Segmentation, Machine Learning to name a few.

I am currently a Post-Doctoral Research Fellow at University of California, Irvine with the prestigious Fellowship Award received from the Belgian-American Educational Foundation (BAEF).

I received my PhD degree in Computer Science Engineering at Ghent University, Belgium in 2017 with a thesis on "Adaptive Routing Algorithms in Networks-on-Chip", and stayed as a Post-Doctoral Researcher at the Department of Electronics and Information Systems until Dec. 2019.

I am the recipient of the Best Paper Award at the 11th International Workshop on Network-on-Chip Architectures (NoCArc) in Oct. 2018. Moreover, I serve as the TPC member and reviewer of several international conferences and journals.

My research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design for embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. In 2017, I have been elevated to the grade of IEEE Fellow “for contributions to energy-efficient computer architectures”. Recently I was European Project Coordinator of the H2020-FET-HPC project ANTAREX-671623 (2015-2018) on "Autotuning and adaptivity approach for energy efficient exascale HPC systems”. I was Project Coordinator of two other European projects: FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). I am an active member of the scientific community and I regularly serve in several international program committees. I annually teach basic and advanced courses on computer architectures and operating systems.