Server memory management is an evolving and challenging area. With growing memory capacity installed per machine and increasing memory DIMM costs, data center planners are facing with huge increase in memory TCO. A plausible direction is to categorize memory accesses by required service level objective (SLO) with the end goal to map lower SLO request to cheaper but low quality memory resource, while using expensive, highest quality memory resource for most critical application request. I work in Linux server memory management to categorize memory access transparent to the user space.

My research interests are in Computer Architecture and Systems and my current research focuses on optimizing GPU architectures for Deep Learning applications, specifically Recurrent Neural Networks. I have been a part of the effort to augment GPGPU-Sim, a widely used GPU simulator, to execute Deep Learning kernels written using NVIDIA's cuDNN and cuBLAS libraries. My research advisor is Prof. Matthew D. Sinclair.

Mary Jane (Janie) Irwin is an Emerita Evan Pugh University Professor in the Department of Computer Science and Engineering at The Pennsylvania State University. She retired in July 2017. Her research and teaching interests include computer architecture, energy-aware and reliability-aware design, emerging technologies, and VLSI systems design and design automation. She is a Fellow of IEEE and ACM and a member of NAE and AAAS. Awards she has received include the 2003 IEEE/CAS VLSI Transactions Best Paper of the Year Award, the 2010 ACM Athena Lecturer Award, the 2012 Ten-Year Retrospective Most Influential ASP-DAC Paper Award, the 2015 FLP Conference 25 Year Paper Recognition, the 2017 ACM/SIGDA Pioneering Achievement Award, and the 2018 EDAA Lifetime Achievement Award. Irwin received her M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign and an Honorary Doctorate from Chalmers University, Sweden.htt

I am Shivani Shah, completed my Bachelor of Technology majoring in Information and Communication Technology from School of Engineering and Applied Science, Ahmedabad University. Currently, I am Research Scholar at IIIT Banglore. During my graduation, I have done a few projects such as 'Implementation of 8-bit MIPS processor on FPGA' (Coding Language: Verilog, Tool: Xilinx). I did my final year project on designing ‘Reduced Hardware Hybrid Branch Predictor’ at Ahmedabad University. Control Block is one of the major parts of any computer architecture, I focused on designing hybrid hardware, a combination of 1-bit predictor and 2-bit predictor, but hardware only of 2-bit predictor which drastically optimized the hardware requirements without compromising processor speed. So right now I have done instruction-level parallelism.