Evey Liu recently finished her undergraduate study at the University of Waterloo for Computer Engineering. She will begin graduate school at the University of Toronto with supervisor Natalie Enright Jerger in January 2019. She is passionate about generic computer architecture and is open to explore different specializations within the field.

Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne.

My research focuses on bridging the gap between software and hardware with the purpose of building efficient circuits for Field Programmable Gate Arrays (FPGAs). I develop new high-level synthesis (HLS) techniques: the purpose is to generate hardware designs from high-level programming languages and to enable software developers to build efficient accelerators. I aim to change the HLS paradigm so that the produced circuits share key features with modern superscalar processors and are able to handle important classes of irregular and control-dominated applications.

I am grateful to have received the Google PhD Fellowship, the EPFL EDIC Fellowship, and the Google Anita Borg (Women Techmakers) Scholarship.

McKee received her bachelor’s degree in Computer Science from Yale University, master’s from Princeton University, and doctorate from the University of Virginia. Her dissertation advisor was Bill Wulf, with whom she worked on memory systems architecture. Together they coined the now-common term the “memory wall” to describe a situation in which processors are always waiting on memory, and CPU performance is therefore entirely limited by memory performance.

Before graduate school, McKee worked for Digital Equipment Corporation and Microsoft Corporation. She has also held internships at Digital Equipment Corporation’s Systems Research Center (now HP Labs) and the former AT&T Bell Labs. McKee worked as a Post-Doctoral Research Associate in the University of Virginia Computer Science Department for a year after graduating (waiting for the chip to come back from fab) and as a Computer Architect at Intel’s Microcomputer Research Lab in Oregon for the next two years. During her time at Intel, she also taught at the Oregon Graduate Institute and Reed College. McKee was a Research Assistant Professor at the University of Utah’s School of Computing from 1998 to 2002, where she worked on the Impulse Adaptable Memory Controller project. She joined Cornell University’s Computer Systems Lab within the School of Electrical and Computer Engineering in 2002. She moved to the Department of Computer Science and Engineering at Chalmers University of Technology in 2008, and she became the C. Tycho Howle endowed chair within the Holcombe Department of Electrical and Computer Engineering at Clemson University in 2018. She spent the 2017 calendar year on sabbatical at Rambus Labs in Sunnyvale, CA.

Her research has historically focused mainly on analyzing application memory behavior and designing more efficient memory systems together with the software to exploit them. Achieving this broad objective requires developing new underpinnings for system understanding, and thus she and her students and collaborators have developed new approaches to performance analysis; built scalable tools for application analysis and system modeling; designed architectures to enable more comprehensive system introspection and analyses; designed efficient memory systems for HPC and embedded platforms; and automated memory optimizations for HPC applications.

Natalie Enright Jerger is the Canada Research Chair in Computer Architecture and a Professor of Electrical and Computer Engineering at the University of Toronto. She is currently serving as the Director of the Division of Engineering Scinece at the University of Toronto. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008, respectively. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal recipient and the 2015 Borg Early Career Award winner. She served as the program co-chair of the 7th Network-on-Chip Symposium, as the program chair of the 20th International Symposium on High Performance Computer Architecture and as program co-chair for the International Conference on Architectural Support for Programming Languages and Operating Systems in 2023. She is currently serving as the ACM SIGARCH Chair. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. She is also passionate about increasing the representation of women in computing, particular in computer architecture. She is the former chair of the organizing committee for the Women in Computer Architecture group (WICARCH). In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. Her research has been supported by NSERC, Intel, CFI, AMD and Qualcomm.