I am a PhD candidate in the Electrical and Computer Engineering department at Carnegie Mellon and a member of the ABSTRACT research group led by Professor Brandon Lucia. My research interests include computer architecture and hardware/software codesign for resource constrained, embedded devices. My current research focuses on programming and execution models for intermittently powered, energy harvesting devices.

Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne.

My research focuses on bridging the gap between software and hardware with the purpose of building efficient circuits for Field Programmable Gate Arrays (FPGAs). I develop new high-level synthesis (HLS) techniques: the purpose is to generate hardware designs from high-level programming languages and to enable software developers to build efficient accelerators. I aim to change the HLS paradigm so that the produced circuits share key features with modern superscalar processors and are able to handle important classes of irregular and control-dominated applications.

I am grateful to have received the Google PhD Fellowship, the EPFL EDIC Fellowship, and the Google Anita Borg (Women Techmakers) Scholarship.

Amila received her Bachelor's and Master's Degrees from the University of Sarajevo in Electrical Engineering within Computer Science and Informatics Department in 2006, 2009, respectively. In academic year 2007/2008 she received Fulbright Visiting Student Award and joined Embedded Systems and Architectures Lab at University California, Riverside as Junior Researcher. In 2010, she spent 1 month at Faculty of Electrical Engineering, University of Ljubljana as a visiting academic. Then, she received MEXT scholarship in 2010 and spend 3 and half years in beautiful Tokyo, where she completed her Ph.D. at Keio University in 2013.

Her primary area of interest is Computer Architecture, including Reconfigurable Architectures, High Performance Computing and Heterogeneous Computing. Her past research mainly focused on finding new ways to accelerate compute-intensive parts of an algorithm by means of offloading it to an FPGA. The challenge is to take advantage of knowledge about an architecture and adapt the algorithm to the architecture rather than the other way around. Her PhD research focused on developing architectures and methodologies that help to reduce the execution time of Cyclic Redundancy Check algorithms, particularly those implemented using FPGAs, and iSCSI protocol implementation.

In recent years, she has expanded her research to include Digital Signal Processing, Computer Vision, Image Segmentation, Machine Learning to name a few.

Harini Muthukrishnan is a final year Ph.D. Candidate at the University of Michigan where she is advised by Prof. Tom Wenisch. Her research focuses on improving strong scaling in multi-GPU systems by optimizing fine-grained transfers and is in collaboration with Systems Architecture Research Group at NVIDIA Research.