The 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA’25) was held from March 1 to 5, 2025 in Las Vegas, USA. Co-located with PPoPP, CGO, and CC as part of the “Parallel Programming, Architecture and Compilation (PARC)” event, HPCA’25 received a record 534 submissions. Over 100 research papers were accepted—resulting in an acceptance rate of approximately 20%—making this one of the largest HPCA editions to date. The conference featured multiple keynote speeches and award ceremonies, while continuing its commitment to reproducibility by advancing the Artifact Evaluation (AE) process.
Workshops and Tutorials
On the first day of March, a series of workshops and tutorials were held, focusing on quantum computing in HPC, deep learning benchmarks, hardware failure prediction, and AI networking technologies. The Networking Workshop explained RDMA programming, network management infrastructure and outlined the domain-specific challenges associated with the design of these systems. Solutions to these challenges, along with sample performance metrics, were presented.
The second day also featured a number of presentations of particular interest, such as secure computing, quantum computer, energy efficient ML and computing systems resilience to hardware faults, which focused on modelling and measuring the effects of silicon defects and errors. XiangShan once again presented the microarchitecture and design concepts of the XiangShan processor, while also providing hands-on development with typical use cases on XiangShan.
Talk on Computing Systems Resilience @Hardware Faults Workshop
Keynote Sessions
The keynote sessions featured distinguished speakers, each delivering a keynote organized by one of the three hosting conferences, challenging the community to tackle critical issues in high-performance computing.
Charles E. Leiserson, in a keynote organized by PPoPP, highlighted the increasing significance of software performance engineering as Moore’s Law slows. He stressed that optimizing code—through techniques like parallel computing, caching, and vectorization—has become crucial for efficient resource utilization. Charles emphasized that performance is money, the currency for computing, which can be exchanged for other vital properties such as security and reliability, positioning it as a cornerstone of future software development. He encouraged the PPoPP community to spearhead this shift, suggesting a redefinition of PPoPP to “Principles and Practice of Performance Programming” to embrace a wider focus on performance optimization.
John Regehr, in a keynote organized by CGO, delved into the trade-offs inherent in compiler development. He pointed out that while building correct compilers is feasible, factors like optimization, compilation speed, and adherence to language standards often take priority. John underscored the economic and engineering challenges involved and urged the community to reconsider compiler design and maintenance strategies to better address these competing priorities.
Cliff Young, in a keynote organized by HPCA, tackled the complexities of scaling machine learning systems. Drawing from his experience with Google’s Tensor Processing Units (TPUs), he explored essential algorithmic components like matrix multiplication and attention, and the resulting challenges of scale and reliability. Cliff called for interdisciplinary collaboration across hardware design, compiler technology, and parallel algorithms to propel advancements in AI and computing amidst the rise of massive models.
Main program
HPCA’25 accepted 113 research papers for the main track, alongside 5 industrial papers and 3 select presentations from IEEE Computer Architecture Letters (Best of CAL). These contributions were organized into various sessions across 3 (sometimes 4) parallel tracks. In terms of topics, roughly one-third of the papers focused on accelerator architectures, another third on traditional computer architecture subjects (such as microarchitecture, caches, large-scale parallel processing, networks-on-chip, and simulation), while the remaining papers addressed emerging areas including quantum computing, security, and memory systems. This distribution reflects the continued evolution of high-performance computing research towards a diverse range of themes.
Building on the success of its introduction at HPCA’22, HPCA’25 further promoted research reproducibility by continuing its Artifact Evaluation process. This year HPCA’25 has 3 AE chairs and 33 student members of AE committee. The artifacts were assessed in accordance with ACM reproducibility standards, with evaluations focusing on functionality, usability, and the reproducibility of reported results. This underscores the community’s dedication to openness and reliability in computer architecture research, and we look forward to even broader engagement in future editions.
A Snapshot of the Main Program Session
Awards Luncheon
The awards lunch on Tuesday was a heartfelt and inspiring gathering, as the community took time to remember Derek Chiou and Sally McKee while listening to their experiences and contributions. The ceremony then moved to recognizing outstanding contributions across various categories. Each award started with a brief introduction by the respective chairs, followed by the announcement of the winners.
The Best Paper Award went to “DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency” by Jovan Stojkovic et al. (from the University of Illinois at Urbana-Champaign and Microsoft)., with honorable mentions for “UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures” by Tongxin Xie et al. (from Tsinghua University, HKUST, Chinese Academy of Sciences, and Capital Normal University) and “CORDOBA: Carbon-Efficient Optimization Framework for Computing Systems” by Mariam Elgamal et al. (from Harvard University, and Meta).
In the Artifact Evaluation category, “QPRAC: Towards Secure and Practical PRAC-Based Rowhammer Mitigation using Priority Queues” and “Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions” earned Distinguished Artifact Awards, while “Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing” received an honorable mention.
The IEEE Fellow class of 2025 honored Aamer Jaleel, John Kim, and Rajasekaran Swaminathan for their groundbreaking work, while the ACM Fellows class of 2025 recognized Fred Chong and Dhabaleswar K. Panda for their influential contributions. Finally, the Test of Time Award went to “Caches and Hash Trees for Efficient Memory Integrity Verification” by Blaise Gassend et al. (from Massachusetts Institute of Technology), a testament to its lasting impact on secure computing. Big congratulations to all the awardees!
Best Paper Award goes to UIUC and Microsoft. Congratulations!
Excursion
The HPCA took us on a tour of the interior of the spectacular Sphere, accompanied by live music with fabulous food and souvenirs. With hundreds of people in attendance, it was an excellent networking opportunity for professionals in various domains. I particularly appreciated the chance to connect with my peers.
Excursion venue: The Las Vegas Sphere
Acknowledgments
I would like to thank my students, Jiajun Luo, Yuchen Fan, Yu Jin, Shunyu Mao for helping me cover all the great events happening at HPCA 2025. Image credits go to my students and HPCA’25 conference. A special thanks to Dmitry Ponomarev for his editorial service.
About the Author
Shuwen Deng is an Assistant Professor in the Department of Electronics Engineering at Tsinghua University. Her research focuses on computer architecture, networks and hardware security.
Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.
