Hardware and architecture security remained a hot research topic in the first half of 2021, with new contributions appearing in architecture, security and systems conferences. Some of these 2021 papers were overviewed in our earlier blog post, here we focus on more recently accepted papers. We overview two security conferences (S&P’21 and Usenix Security’21) and one systems conference (EuroSys’21). At the end, we briefly summarize 2021 security papers in architecture conferences (HPCA, ASPLOS and ISCA). Part II of this blog theme covering the second part of 2021 will appear at the end of the year.
S&P 2021
Transient execution attacks continued to evolve with new variations and formalisms. Cache Out attack exploits its undocumented interaction between the L1 Cache and the line fill buffer on Intel processors, where the data evicted from L1 sometimes ends up in the fill buffers. Exploitation of this path allows the attackers to bypass previously proposed protections from leaky fill buffers. Hardware-software contracts for secure speculation paper presents a formal framework for principled hardware-software co-design that recognizes the trade-off between performance impact of defensive measures and the ability to execute a larger number of programs securely under speculation. The hardware-software contracts specify which program executions can be distinguished by attackers: they are expressed using ISA, the model of a microarchitecture, and the model of potentially leaky datapath components. This paper makes an important step towards formalizing our understanding of transient execution attacks and what it means to support secure speculation.
Timing attacks evolved beyond caches, TLBs, branch predictors and other on-chip structures. Invisible Probe paper presents a timing attack on PCIe interconnect exploiting bus congestion. If a victim’s activity involves moving data over PCIe, the adversary accessing another device can infer secret information by measuring bus congestion.
Randomized caches have been a subject of active research recently, including both new secure cache designs and attacks against these new defenses. This paper describes vulnerabilities of several current randomization schemes and proposes new approaches to make randomization more secure. It appears that the debate on this topic is far from over.
The concept of building a zero-knowledge processor has been significantly advanced in this paper, where the authors built a prototype capable of executing standard Linux programs, including a compiler toolchain, an efficient ORAM BubbleRAM and its extension to multi-level caching.
USENIX Security 2021
Several papers of interest to our community have been accepted to USENIX Security Symposium 2021. Virtual Secure Platform demonstrates a prototype of a 5-stage in-order pipelined processor to support execution over fully-homomorphic encryption to support secure multi-party computation. The authors designed a custom ISA and implemented a complete toolchain including a C compiler.
VoltPillager showed how a hardware-based voltage glitching attack can be launched against Intel SGX. Specifically, the authors developed a low-cost tool for injecting messages on the bus connecting the CPU and the voltage regulator, allowing a precise control of the CPU core voltage. This tool is then used to mount fault injection attacks on SGX.
Another paper explored the feasibility of microcode trojans in an embedded processor. The authors demonstrated that despite having complete control over the hardware, design of meaningful trojans is not straightforward. They also showed, using several case studies, how one still can design trojans posing real security risks despite the challenges.
Lord of the Ring(s) demonstrated practical side-channel attacks that leverage contention on on-chip interconnects. To develop the attack, the authors addressed several challenges, including reverse-engineering of the protocols for ring interconnects and dealing with the measurement noise.
To continue advances in rowhammer attacks, SMASH describes a synchronized many-sided hammering technique to trigger bit flips in DDR4 chips from JavaScript. The attack uses several innovations: it exploits the knowledge of cache replacement policies, decomposes n-sided rowhammer into multiple double-sided pairs, and carefully schedules cache hits and misses. The authors demonstrate a full JavaScript exploit that can compromise a FireFox browser in about 15 minutes.
Several recent cache side-channel attacks have been performed directly from JavaScript code in browsers. Prime+Probe 1, JavaScript 0 investigates the minimal features that are required to mount microarchitectural attacks in browsers, and the feasibility of such attacks in restrictive environments. The authors then develop a new attack that exclusively relies on CSS and HTML, and works across hardware platforms even when the script execution is entirely blocked.
Mirage presents a practical fully-associative cache design for mitigating side-channel attacks. Since the victim candidates are selected randomly among all cache lines, the set conflicts are avoided. To keep complexity at manageable levels for large last-level caches, the authors propose to decouple placement and replacement to retain set-associative lookups. They also use pointer-based indirection from tag-store to data-store to allow global evictions of randomly selected lines.
CURE presents an architecture where different types of enclaves are supported by the system, instead of “one-size-fits-all” design supported by current trusted execution environments (TEEs). These include enclaves that provide vertical isolation at all execution privilege levels, enclaves that provide isolated execution to unprivileged applications, and enclaves that allow isolated execution environments that span multiple privilege levels. The authors also show how hardware resources can be exclusively assigned to enclaves and demonstrate a RISC-V prototype of their design.
EuroSYS 2021
Several papers of interest to our community were presented at EuroSys 2021. DMA code injection vulnerabilities in the presence of IOMMU are characterized and exploited in this paper. The authors then present a new class of compound DMA attacks, where the vulnerability attributes are initially incomplete, but can be obtained by exploiting OS behavior.
Rkt-io addresses performance inefficiencies and security risks of modern TEEs that prevent them from running I/0 intensive applications with high performance networking and storage requirements. The authors propose a direct user-level storage and networking I/O stack specifically designed to work with TEEs. The proposal includes polling for I/O events directly instead of relying on interrupts and avoiding data copying by mapping DMA regions in the untrusted host memory.
HPCA/ASPLOS/ISCA 2021
Our main conferences in 2021 also remained vibrant with security papers. Since the readers of this blog are more familiar with these conferences, we only provide a high-level summary, for completeness. HPCA 2021 featured two security sessions with 8 papers. Topics include compressed encryption counters, ORAM optimizations, acceleration of homomorphic encryption, new models for speculation-based attacks, thermal attacks in data centers, cache timing attacks on GPU, rowhammer defenses and securing metadata in non-volatile memories.
ASPLOS 2021 also featured two security sessions with a total of six papers, with topics covering kernel control-flow hardening, microarchitectural weird machines, hardware-enforced secure message queues, a new cache-based covert channel, a new transient execution attack, and a defense against microarchitectural replay attack. Microarchitectural weird machines essentially extend side-channel and timing attacks to a new frontier, allowing attackers to perform arbitrary computations by means of execution side-effects and conflicts over various hardware structures. Speculative interference attack shows vulnerability of previously proposed invisible speculation schemes, because secrets accessed by misspeculated younger instructions can change the order of bound-to-retire loads, making secret-dependent changes to the cache. New defenses should therefore consider this attack variation.
ISCA 2021 featured three security sessions. The papers addressed a wide range of topics, including a study of possible ways microarchitecture can leak secrets, information leakage through micro-op caches, a new defense from cache side-channel attacks, a pre-silicon framework for discovering transient execution vulnerabilities, a technique to obfuscate power side-channels, low-overhead memory safety, covert channels on integrated CPU-GPU systems, covert channels through current management and protection from pointer integrity attacks.
In summary, many excellent works have been published in the first half of 2021, covering new attacks, defenses, security models and formalisms. Looking forward to more exciting results, and we will return with the second part of this review at the end of the year.
About the author: Dmitry Ponomarev is a Professor and Associate Chair in the Department of Computer Science at Binghamton University. His research interests are in computer architecture, with a recent emphasis on security.
Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.
