In an earlier blog post, we summarized advances in hardware and architecture security research in the early part of 2021; this post highlights contributions that appeared in the later part of 2021 that are of interest to our community. In this post, we focus on papers from MICRO’21, CCS’21, ACSAC’21, OSDI’21, and recent papers accepted to major security conferences to be held in 2022. We also highlight a new conference dedicated to secure execution environments — IEEE Symposium on Secure and Private Execution Environment Design (SEED). The first edition of SEED was held in September of 2021.
MICRO’2021
MICRO’21 featured three security sessions with a combined 14 papers (out of the total 94 papers presented at the conference). This again demonstrates that security remains a hot research area in our community. The topics covered in these papers range from securing accelerators, to efficient capability-based systems, to protection from transient execution attacks, to better security models.
IceClave is a new framework to securely offload computations to SSD. The authors first investigate attacks that are possible without security measures, and then demonstrate how to build a trusted execution environment (TEE) to perform in-storage computing. DarKnight is a secure framework for large DNN training that relies on cooperative execution between TEE and accelerators, such as GPUs, which perform the bulk of computations. The idea is to use a customized data encoding to obfuscate inputs to the TEE. The obfuscated data is then offloaded to GPUs for fast computation. F1 is a programmable accelerator for fully-homomorphic encryption that is capable of executing full programs. Cryptographic Capability Computing (C3) is the stateless memory safety mechanism that does not require additional metadata storage besides what is encoded in a 64-bit pointer..
UC-Check demonstrated that micro-operation caches can leak information through a timing channel, and this can present a security vulnerability. The authors reverse-engineer the micro-op cache operation, describe concrete attacks that exploit this vulnerability, and present possible mitigations. Another type of a microarchitectural timing channel exploits shared, on-chip interconnect on a GPU. In GPUs, the interconnect bandwidth is shared between neighboring cores, making it possible to exploit the resulting contention.
A systematic approach to detecting side-channel vulnerabilities is to use information-flow analyses with abstract models that express the attacker’s view of the system in terms of “observations”, i.e. parts of the program state that may be leaked during execution. Observation refinement is a technique to guide the exploration of the state space to reduce its size. GhostMinion introduced the concept of Strictness Ordering, a new constraint system that eliminates transient execution attacks, while still allowing speculation and data forwarding between dependent instructions. The authors also describe cache designs to support Strictness Order at a small cost to performance. Speculative Privacy Tracking is a design for protecting from transient execution attacks based on the observation that it is safe to speculatively execute a potential secret transmitter instruction if the operands were already leaked during non-speculative execution. This approach relaxes some conditions inherent in previous designs and results in better performance.
Two papers addressed rowhammer vulnerabilities. One of these papers focused on demonstrating how the RowHammer effects vary with chip temperature, aggressor row active time and the physical location, using experimental characterization with modern DDR3 and DDR4 chips. The second paper presented U-TRR that is based on the observation that data retention failures in DRAM create a side channel, leaking information about TRR refreshes. That, in turn, makes it possible to shape attack access patterns in a way that defeats existing TRR-based defenses.
Several papers addressed security of non-volatile and persistent memories. Soteria showed that the error sensitivity of security metadata is higher than that of the general data and they proposed a scheme to increase error tolerance of security metadata by lazy duplication. Bonsai Merkle Forests attempt to reduce the performance overhead of securing persistent memory. The idea is to split an integrity checking tree into multiple trees with the tree roots maintained in the on-chip non-volatile metadata cache. Dolos demonstrated how to improve performance of persistent applications in a system with ADR-supported persistent memory.
Security and Systems Conferences (CCS’21, OSDI’21, ACSAC’21, USENIX’22, S&P’22)
New vulnerabilities in commercial trusted execution environments continue to be discovered. SmashEx attack (CCS’21) demonstrated that asynchronous exception handling in SGX enclaves can be prone to re-entry vulnerabilities, leading to exploits that cause arbitrary disclosure of enclave private memory and subsequent code-reuse attacks. Another work (ACSAC’21) described security issues of TLB management on AMD SEV processors and demonstrated a novel TLB Poisoning attack against SEV virtual machines. Another ACSAC’21 paper described a side-channel vulnerability of System-level Cache in ARM-based systems-on-chip, allowing website fingerprinting attacks. Penglai (OSDI’21) described a software-hardware co-design to support enclave computing that can scale to thousands of concurrent enclaves with high performance and strong security guarantees. The design is based on two new hardware primitives: a Guarded Page Table to support page-level secure memory isolation and Mountable Merkle Tree to support scalable memory integrity protection.
Recent attacks exploiting SMT processors put in question the viability of multithreading despite its ability to achieve high throughput in an area-efficient manner. SecSMT (Security’22) provides comprehensive analysis of contention-based security vulnerabilities in an SMT processor and presents several mitigation strategies to reduce side-channel leakage while maintaining performance. Most recent side-channel attacks have been focused on Intel processors. Prefetch-based attacks on AMD processors (Security’22) can leak even more information, as the timing and power variations of the prefetch instruction can be observed from the user space. Another important problem is how to develop new microarchitectural attacks. This paper (Security’22) described a new approach to rapid attack prototyping that involves two new publicly available frameworks: libtea provides an API to abstract platform-specific details such as native timers, while SCFirefox exposes this API to JavaScript to explore browser-based attacks. Elasticlave (Security’22) presented a memory model for enclaves that allows sharing memory with other enclaves. vSGX (S&P’22) described a novel design to virtualize the execution of an Intel SGX enclave on top of AMD SEV system, this is a step towards ensuring compatibility of TEEs across different platforms. SpecHammer (S&P’22) showed how to combine Spectre and Rowhammer attacks to create new transient execution exploits.
SEED’21
Finally, we present a short summary of SEED 2021 – a new symposium dedicated to trusted execution environments. General Chairs Yan Solihin and Jakub Szefer and Program Chairs Guru Venkataramani and Yinqian Zhang did an excellent job putting together a program consisting of two keynote talks (by Milos Prvulovich and Ahmad-Reza Sadeghi) and six sessions with 26 papers. The paper sessions included regular papers, work-in-progress papers and ”seeds-of-SEED”. The papers covered a wide range of topics – transient execution attacks, code reuse attacks, secure cache designs, resource-sharing attacks on the cloud, memory integrity checking and access pattern obfuscation schemes, confidential computing and benchmarking for privacy-aware computing, to name a few. We hope that SEED will become an annual event, providing architecture security researchers with a new venue to submit their papers.
In summary, the area of hardware and architecture security continues to thrive with a large number of papers in architecture, security and systems venues, and even new conferences! We look forward to new ideas and exciting results in the rest of 2022.
About the author: Dmitry Ponomarev is a Professor and Associate Chair in the Department of Computer Science at Binghamton University. His research interests are in computer architecture and security.
Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.
