by Mingyu Gao on Dec 21, 2021 | Tags: Accelerators, Graph Mining
Graphs have long been treated as a challenging data type in the system and architecture community, due to excessive random accesses from the irregular graph structures and significant load imbalance from the power-law degree distribution. Beyond traditional graph...
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by ASPLOS Steering Committee on Nov 30, 2021 | Tags: Conference, Policy, Reviewing
TL;DR The ASPLOS Steering Committee is considering two changes to the ASPLOS submission process: 1) three submission deadlines spread over the year, and 2) the possibility for papers near acceptance to be revised and resubmitted. This proposal outlines these changes....
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by Tamara Lehman on Nov 3, 2021 | Tags: Conference, Virtual Meetings
Like every other conference in the year 2021, thanks to the COVID-19 pandemic, MICRO-54 is once again being held in a virtual format over the Whova platform. While I miss the personal interactions you get with an in-person conference, I do appreciate the benefits of...
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by Phillip Stanley-Marbell on Oct 19, 2021 | Tags: Accelerators, Approximate Computing, Numerical Format, Sensors, Uncertainty
In Part 1 of this two-part post, I looked at some of the existing and possible avenues for computer architecture research relating to tracking uncertainty in computations, using the blackscholes benchmark from the PARSEC suite of computer architecture research benchmark applications as a working example. In this post, I’ll outline some existing and possible future paths for computer architects in computation with uncertainty. Just as architectural support and microarchitectural implementations of floating-point number representations improved the ease of implementation of real-valued computations, architectural and microarchitectural support for representations of uncertainty could enable new approaches to trustworthy computation on empirical data.
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by Elba Garza on Oct 15, 2021 | Tags: Academia, CASA, Mentoring, Students
With MICRO upon us, I would like to take time to reflect on the events running up to the establishment of CASA, or the Computer Architecture Student Association. This month we will be celebrating our first anniversary as an active organization! We at CASA, feel we...
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by Caroline Trippel on Sep 27, 2021 | Tags: formal methods, program synthesis, Security
This blog post samples a growing body of research which leverages formal methods techniques to solve computer architecture challenges. While certainly not exhaustive, it is meant to serve as a starting point for further reading and brainstorming. Constructing Formal...
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by Sergey Blagodurov, Mike Ignatowski, Valentina Salapura on Sep 22, 2021 | Tags: Accelerators, Coherence, Datacenters, Interconnects, Memory, Networking, Systems
Despite being hidden from the end user, datacenters are ubiquitous in today’s life. Massive datacenter installations are the driving force behind social networking, search, streaming services, e-commerce, cloud, and the gig economy. Today’s datacenters are as...
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by Simla Burcu Harma, Mario Drumond, Babak Falsafi on Sep 20, 2021 | Tags: Accelerators, Machine Learning, Numerical Format, Tools
DNN training is emerging as a popular compute-intensive workload. This blog post provides an overview of the recent research on numerical encoding formats for DNN training, and presents the Hybrid Block Floating-Point (HBFP) format which reduces silicon provisioning...
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by Gururaj Saileshwar on Sep 15, 2021 | Tags: Cache, Computer Architecture, Randomization, Security
There is a battle ongoing in the realm of secure caches. Cache side-channels are a serious security problem as they allow an attacker to monitor a victim program’s execution and leak sensitive data like encryption keys, confidential IP, etc. A potent class of such...
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by Minsoo Rhu on Sep 9, 2021 | Tags: Datacenters, Emerging Technology, Interconnects, Memory, Memory Disaggregation, Processing-in-Memory
The Memory (Bandwidth and Capacity) Wall The “memory wall” problem, originally coined by Wulf and McKee in the 1990s, pointed out that the rate of improvement in microprocessor performance far exceeds the rate of improvement in DRAM memory speed. Such trend rendered...
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