Opportunities and Challenges of Computing in Die-Stacked Image Sensors
Some of the most exciting applications on the horizon such as autonomous machines, Augmented/Virtual Reality, space exploration, and precision medicine rely on image sensing — at different scales. While conventional CMOS image sensors are responsible for only...
Performance Counters I’d Like to See – Part II
Part 1 of this article discussed a reliable elapsed-time counter design. This Part 2 discusses the four counters needed to make sense of unexpectedly slow execution: total issue slots, issue slots filled with instructions, filled issue slots that actually issue, and...
Performance Counters I’d Like to See – Part I
Introduction I created the performance counters found in almost all CPU chips today, initially in the DEC Alpha 20164 and DEC NVAX chips, announced in early 1992 and late 1991 respectively, but running internally earlier. I made some mistakes, focusing on what events...
Response to Change in the ASPLOS Conference Submission Process
In late November, the ASPLOS Steering Committee published a proposal to change the paper submission process for ASPLOS by introducing three deadlines per year and the possibility of resubmitting a paper. The Steering Committee asked the ASPLOS community for its...
Algorithm Evolution and Hardware Acceleration of Graph Mining
Graphs have long been treated as a challenging data type in the system and architecture community, due to excessive random accesses from the irregular graph structures and significant load imbalance from the power-law degree distribution. Beyond traditional graph...
A New ASPLOS Conference Submission Process
TL;DR The ASPLOS Steering Committee is considering two changes to the ASPLOS submission process: 1) three submission deadlines spread over the year, and 2) the possibility for papers near acceptance to be revised and resubmitted. This proposal outlines these changes....
MICRO 2021 Trip Report
Like every other conference in the year 2021, thanks to the COVID-19 pandemic, MICRO-54 is once again being held in a virtual format over the Whova platform. While I miss the personal interactions you get with an in-person conference, I do appreciate the benefits of...
Uncertainty in Computation and Computer Architectures, Part 2
In Part 1 of this two-part post, I looked at some of the existing and possible avenues for computer architecture research relating to tracking uncertainty in computations, using the blackscholes benchmark from the PARSEC suite of computer architecture research benchmark applications as a working example. In this post, I’ll outline some existing and possible future paths for computer architects in computation with uncertainty. Just as architectural support and microarchitectural implementations of floating-point number representations improved the ease of implementation of real-valued computations, architectural and microarchitectural support for representations of uncertainty could enable new approaches to trustworthy computation on empirical data.
Happy Birthday, CASA! A Retrospective
With MICRO upon us, I would like to take time to reflect on the events running up to the establishment of CASA, or the Computer Architecture Student Association. This month we will be celebrating our first anniversary as an active organization! We at CASA, feel we...Subscribe
